公开(公告)号：US06543674B2

公开(公告)日：2003-04-08

申请号：US09778658

申请日：2001-02-06

申请人： Michael G. Lee ,  Connie M. Wong ,  Wen-chou Vincent Wang

发明人： Michael G. Lee ,  Connie M. Wong ,  Wen-chou Vincent Wang

IPC分类号： B23K3102

CPC分类号： H01L24/02 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1601 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/0475 ,  H05K2203/111 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump. A semiconductor assembly including a semiconductor device having an electrode pad coupled to a semiconductor substrate and comprising an electrode structure defined by a pair of arcuate surfaces generally tangentially terminating in an apex.

公开(公告)号：US06611635B1

公开(公告)日：2003-08-26

申请号：US09295628

申请日：1999-04-20

申请人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

发明人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

IPC分类号： G02B612

CPC分类号： H01L24/96 ,  G02B6/06 ,  G02B6/12002 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/43 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/82 ,  H01L25/167 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0274 ,  H05K1/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.

摘要翻译： 公开了将薄的光电子层的器件和/或材料集成到一起，这增加了用于芯片安装的空间，并且通过消除光电子器件和光波导之间的光学对准的难度来降低总系统成本。 光电子器件与厚度为1〜250μm的超薄聚合物层的光波导集成。

公开(公告)号：US06239485B1

公开(公告)日：2001-05-29

申请号：US09315785

申请日：1999-05-20

申请人： Michael G. Peters ,  Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William Chou ,  Michael G. Lee ,  Solomon Beilin

发明人： Michael G. Peters ,  Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William Chou ,  Michael G. Lee ,  Solomon Beilin

IPC分类号： H01L2312

CPC分类号： H05K1/0219 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/144 ,  H05K3/20 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/10378 ,  H01L2924/00

摘要： An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.

摘要翻译： 一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。 本发明的插入器包括信号芯和外部电源/接地连接外壳。 这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。 信号芯由位于两个电介质层之间的导电电源/接地平面形成。 在每个电介质层上形成图案化的金属层。 两个金属层通过通孔或后处理相互连接。 导电功率/接地面用于减少形成在两个图案化金属层上的信号线之间的信号串扰。 电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。 电源/接地线圈的上下基板由两面具有图案化金属层的电介质膜形成，图案化层通过通孔或后工艺连接。 两个电源/接地包覆基板可以分开地形成，或者可以从弯曲成所需形状（例如，“U”形状）的一个基板形成。 两个电源/接地基板相对于信号芯线保持正确的对准，并通过也连接到信号芯的中间电源/接地平面的边缘连接器彼此保持。

公开(公告)号：US5916453A

公开(公告)日：1999-06-29

申请号：US717266

申请日：1996-09-20

申请人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： H01L21/3105 ,  H01L21/321 ,  H05K3/24 ,  H05K3/46 ,  C25F3/16

CPC分类号： H01L21/31053 ,  H05K3/4647 ,  H05K2203/025 ,  H05K2203/0733 ,  H05K3/243

摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构的形成位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于所述结构 在低于结构顶部的平面内。 然后在平坦化层的低区域上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，并且优选地，结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。

公开(公告)号：US06733685B2

公开(公告)日：2004-05-11

申请号：US09881514

申请日：2001-06-12

申请人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： Solomon I. Beilin ,  Michael G. Lee ,  William T. Chou ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： B44C122

CPC分类号： H01L21/31053 ,  H05K3/243 ,  H05K3/4647 ,  H05K2203/025 ,  H05K2203/0733

摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构将被形成的位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于 在低于结构顶部的平面内。 在平坦化层的低面积上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，优选结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。

公开(公告)号：US06662443B2

公开(公告)日：2003-12-16

申请号：US09935378

申请日：2001-08-22

申请人： William T. Chou ,  Solomon Beilin ,  Michael G. Lee ,  Michael G. Peters ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon Beilin ,  Michael G. Lee ,  Michael G. Peters ,  Wen-chou Vincent Wang

IPC分类号： H01K310

CPC分类号： H05K3/423 ,  H05K3/0035 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.

摘要翻译： 公开了一种制造多层互连衬底的方法。 在一个实施例中，该方法包括提供具有电介质基底的结构，其具有第一基本上平坦的表面和相对的第二基本上平坦的表面。 第一导电层设置在电介质基板的第一基本上平坦的表面上，并且在第一导电层和电介质基板之间存在界面。 在该结构中形成盲通孔部位，并且通过电介质基板到第一导电层和电介质基板之间的界面。 盲孔通过电镀工艺填充导电材料。

公开(公告)号：US5722162A

公开(公告)日：1998-03-03

申请号：US541219

申请日：1995-10-12

申请人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H05K3/10

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

摘要翻译： 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。

公开(公告)号：US06690845B1

公开(公告)日：2004-02-10

申请号：US09574422

申请日：2000-05-19

申请人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

发明人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

IPC分类号： G02B612

CPC分类号： H01L24/96 ,  G02B6/06 ,  G02B6/12002 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12104 ,  G02B2006/12107 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/5389 ,  H01L25/167 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/05022 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/73104 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0274 ,  H05K1/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.

摘要翻译： 公开了具有多个光电子（O / E）层的三维光电模块，光信号在一个或多个三维体积内的O / E层之间布线。 在优选实施例中，O / E层设置在彼此之上并且彼此之间，其边缘中的至少一个彼此对准。 至少两个O / E层具有端部靠近对准边缘的波导。 多个Z连接器阵列设置在O / E层之间并且在三维体积内以提供多个Z方向波导。 第一垂直光耦合器将来自一个O / E层中的一个波导的光耦合到Z向波导，并且第二垂直光耦合器将来自Z方向波导的光耦合到第二O / E层中的第二波导。 在另外的优选实施例中，Z连接器阵列的段由保持单元保持。

公开(公告)号：US06343171B1

公开(公告)日：2002-01-29

申请号：US09295813

申请日：1999-04-20

申请人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

发明人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Masaaki Inao ,  Michael G. Lee ,  William Chou ,  Solomon I. Beilin ,  Wen-chou Vincent Wang ,  James J. Roman ,  Thomas J. Massingill

IPC分类号： G02B626

CPC分类号： H01L24/96 ,  G02B6/06 ,  G02B6/12002 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12104 ,  G02B2006/12107 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/82 ,  H01L25/167 ,  H01L31/0203 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0274 ,  H05K1/14 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05664

摘要： Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

摘要翻译： 公开了具有用薄膜有源器件形成在薄层中的电和光互连的光电系统。 在一个实施例中，使用光折射材料在一个基板的边缘和另一个基板的表面之间形成光学连接。 在另一个实施例中，通过将光学膜与第一基板分离并将第一基板和光学膜耦合到位于第二基板上的分离的接收器来进行光学连接。 还公开了采用本发明方面的薄膜光链路模块。

公开(公告)号：US5930890A

公开(公告)日：1999-08-03

申请号：US858192

申请日：1997-04-21

申请人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  David A. Horine ,  David Kudzuma ,  Michael G. Lee ,  Larry Louis Moresco ,  Wen-chou Vincent Wang

IPC分类号： G03F7/26 ,  H01L21/48 ,  H01L23/12 ,  H01L23/52 ,  H05K3/18 ,  H05K3/40 ,  H01K3/10

CPC分类号： H05K3/4007 ,  H01L21/4853 ,  H01L2924/00013 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0577 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

摘要翻译： 通过在基板上形成第一层正性光致抗蚀剂，通过在第一层上软化烘烤该第一层并将其暴露在短时间内，用一个整体电路芯片来形成用于安装诸如集成电路芯片的微电子器件的互连柱， 宽孔径面罩或简单的UV空白洪水曝光。 在不显影第一层的情况下，将第二层正性抗蚀剂涂覆在第一层上，软化，然后用窄孔径掩模曝光。 在第二层的软烘烤期间，光致抗蚀剂化合物中的一些活化剂扩散到第一层的暴露部分，并以这样的方式改变其溶解度，使得当这些层随后显影时，显影剂部分地削弱未曝光 第一层的部分以在光致抗蚀剂中形成具有大致均匀横截面的开口。 然后可以通过电镀填充该开口以产生强大的整体互连柱。