公开(公告)号：US10748878B2

公开(公告)日：2020-08-18

申请号：US16523804

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/40 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L25/18 ,  H01L23/538

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US10573612B2

公开(公告)日：2020-02-25

申请号：US16104720

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US10559495B2

公开(公告)日：2020-02-11

申请号：US16199788

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/304 ,  H01L21/306 ,  H01L23/28 ,  H01L21/768 ,  H01L21/02 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US10481200B2

公开(公告)日：2019-11-19

申请号：US16177917

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/00 ,  G01R31/28 ,  G01R1/073

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US20190198388A1

公开(公告)日：2019-06-27

申请号：US16199788

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/768 ,  H01L23/29 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02041 ,  H01L21/561 ,  H01L21/568 ,  H01L23/298 ,  H01L23/3128

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US20180308785A1

公开(公告)日：2018-10-25

申请号：US16020567

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L23/373 ,  H01L21/56

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US09691746B2

公开(公告)日：2017-06-27

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/367 ,  H01L23/44 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US09515002B2

公开(公告)日：2016-12-06

申请号：US14617375

申请日：2015-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S Gandhi ,  James M. Derderian ,  Sameer S Vadhavkar ,  Jian Li

IPC: H01L21/44 ,  H01L23/34 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L21/78 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/06519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Abstract translation: 用于提供从衬底到热粘合垫的热路径的装置和方法。 热路径可以是热粘合垫的金属延伸部，其设置在形成在热粘合垫下方的背侧钝化层中的通道中，并且可以与下面的基底直接接触。 热路径可以提供从衬底改善的热耗散。

公开(公告)号：US20160343687A1

公开(公告)日：2016-11-24

申请号：US14716176

申请日：2015-05-19

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/373 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3738 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2224/83

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

Abstract translation: 本文公开了具有由半导体材料形成的传热结构的半导体器件组件。 在一个实施例中，半导体器件组件可以包括由半导体衬底形成的热传递结构。 热转印结构包括内部区域，从内部区域突出的外部区域和由内部区域和外部区域限定在外部区域中的空腔。 半导体器件组件还包括在空腔中的第一半导体管芯堆叠，以及附接到热传递结构的外部区域并且在空腔内封装第一半导体管芯堆叠的第二半导体管芯。