公开(公告)号：US20170317098A1

公开(公告)日：2017-11-02

申请号：US15651719

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76 ,  H01L29/7827

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20170054036A1

公开(公告)日：2017-02-23

申请号：US14830517

申请日：2015-08-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L29/792 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract translation: 一些实施例包括具有导电材料的集成结构，导电材料上的选择器件栅极材料以及选择器件栅极材料上的垂直堆叠的导电电平。 垂直延伸的单片通道材料与选择器件栅极材料和导电电平相邻。 单片通道材料包含与选择器件栅极材料相邻的下部段和邻近导电层的上段。 第一垂直延伸区域在单片通道材料的下段和选择器件栅极材料之间。 第一垂直延伸区域包含第一材料。 第二垂直延伸区域位于单片通道材料的上部段和导电层之间。 第二垂直延伸区域包含与第一材料的组成不同的材料。

公开(公告)号：US12250820B2

公开(公告)日：2025-03-11

申请号：US18098019

申请日：2023-01-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock

IPC: H10B43/27 ,  H01L29/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12029032B2

公开(公告)日：2024-07-02

申请号：US18117989

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12010836B2

公开(公告)日：2024-06-11

申请号：US17319246

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Prakash Rau Mokhna Rau

IPC: H10B41/27 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/31111 ,  H01L21/32133 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed.

公开(公告)号：US11569258B2

公开(公告)日：2023-01-31

申请号：US16933693

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Liu Liu ,  David Daycock ,  Rithu K. Bhonsle ,  Giovanni Mazzone ,  Narula Bilik ,  Jordan D. Greenlee ,  Minsoo Lee ,  Benben Li

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L21/32 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20210233922A1

公开(公告)日：2021-07-29

申请号：US17229672

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L27/112 ,  H01L21/67 ,  H01L21/3215 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210091009A1

公开(公告)日：2021-03-25

申请号：US16579577

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Devesh Kumar Datta ,  David Daycock ,  Keen Wah Chow ,  Tom George ,  Justin B. Dorhout ,  Bingli Ma ,  Rita J. Klein ,  John Mark Meldrim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a conductive structure which includes silicon-containing material. A stack is over the conductive structure and includes alternating insulative levels and conductive levels. Channel material pillars extend through the stack and are electrically coupled with the conductive structure. Memory cells are along the channel material pillars. A conductive barrier material is under the silicon-containing material. The conductive barrier material includes one or more metals in combination with one or more nonmetals. An electrical contact is under the conductive barrier material. The electrical contact includes a region reactive with silicon. Silicon is precluded from reaching said region at least in part due to the conductive barrier material. Control circuitry is under the electrical contact and is electrically coupled with the conductive structure through at least the electrical contact and the conductive barrier material.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.