公开(公告)号：US20190067475A1

公开(公告)日：2019-02-28

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L21/425

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US20190067375A1

公开(公告)日：2019-02-28

申请号：US16118110

申请日：2018-08-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/24 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  G11C13/00

Abstract: A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices.

公开(公告)号：US09450024B2

公开(公告)日：2016-09-20

申请号：US15004744

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/24 ,  H01L29/786 ,  H01L29/66 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿着底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。

公开(公告)号：US20160225860A1

公开(公告)日：2016-08-04

申请号：US15095211

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L29/24 ,  H01L29/10 ,  H01L29/06 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US09305929B1

公开(公告)日：2016-04-05

申请号：US14623749

申请日：2015-02-17

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/00 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Abstract translation: 存储单元包括与选择装置串联电耦合的选择装置和电容器。 该电容器包括两个导电电容器电极，其间具有铁电材料。 该电容器具有从电容器电极中的一个通过铁电材料到另一个的本征电流泄漏路径。 存在从一个电容器电极到另一个电容器电极的平行电流泄漏路径。 并联电流泄漏路径与固有路径电路并联，总内阻小于固有路径。 公开其他方面。

公开(公告)号：US09276092B1

公开(公告)日：2016-03-01

申请号：US14516396

申请日：2014-10-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L21/02

CPC classification number: H01L45/1206 ,  H01L21/02532 ,  H01L21/02568 ,  H01L23/535 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/12 ,  H01L29/267 ,  H01L29/66666 ,  H01L29/66969 ,  H01L29/66977 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L43/02 ,  H01L43/10 ,  H01L45/142 ,  H01L45/143

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract translation: 一些实施例包括具有漏极区域和源极区域的晶体管。 导电栅极位于源区和漏区之间。 第一通道材料位于栅极和源极区域之间。 第一通道材料通过一种或多种绝缘材料与栅极间隔开。 第二通道材料位于第一通道材料和源极区之间，并直接接触源区。 第一和第二通道材料是过渡金属硫族化物。 源区和漏区中的一个是孔储存区，另一个是电子储存区。 隧道介电材料可以在第一和第二通道材料之间。

公开(公告)号：US09269899B1

公开(公告)日：2016-02-23

申请号：US14615188

申请日：2015-02-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Marko Milojevic ,  David H. Wells ,  F. Daniel Gealy

IPC: G11C5/12 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/126 ,  G11C5/12 ,  G11C11/221 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally activated conduction activation energy of 0.5 eV to 3.0 eV. A second current path extends from the one electrode to the other and is circuit-parallel the first current path. The second current path exhibits a minimum 100-times increase in electrical conductivity for increasing temperature within a temperature range of no more than 50° C. between 300° C. and 800° C. and exhibits a minimum 100-times decrease in electrical conductivity for decreasing temperature within the 50° C. temperature range. Other embodiments are disclosed.

Abstract translation: 电子设备包括两个导电电极。 第一电流路径从一个电极延伸到另一个电极，并且具有0.5eV至3.0eV的显性热激活传导激活能。 第二电流路径从一个电极延伸到另一个电极并且与第一电流路径电路并联。 在300℃和800℃之间，在不超过50℃的温度范围内增加温度，第二电流路径的电导率最小提高100倍，并且电导率最小降低100倍 用于在50°C温度范围内降低温度。 公开了其他实施例。

公开(公告)号：US09147729B2

公开(公告)日：2015-09-29

申请号：US14189296

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

Abstract translation: 一些实施例包括形成晶体管的方法。 凹部形成为延伸到半导体材料中。 这些凹槽具有内衬有衬垫材料的上部区域，并且具有沿下部区域暴露的半导体材料段。 半导体材料通过暴露的部分进行各向同性蚀刻，该部分将凹陷转变成在较窄上部区域下方具有较宽的较低区域的开口。 栅介电材料沿着开口的侧壁形成。 栅极材料形成在开口之间的开口和半导体材料的开口之间的区域上。 绝缘材料沿着每个开口的中心形成并完全通过栅极材料形成。 栅极材料的一段从一个开口延伸到另一个，并且在开口之间缠绕半导体材料的柱。 该段是晶体管的栅极。 源极/漏极区域形成在栅极的相对侧上。

公开(公告)号：US20150243734A1

公开(公告)日：2015-08-27

申请号：US14189296

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

Abstract translation: 一些实施例包括形成晶体管的方法。 凹部形成为延伸到半导体材料中。 这些凹槽具有内衬有衬垫材料的上部区域，并且具有沿下部区域暴露的半导体材料段。 半导体材料通过暴露的部分进行各向同性蚀刻，该部分将凹陷转变成在较窄上部区域下方具有较宽的较低区域的开口。 栅介电材料沿着开口的侧壁形成。 栅极材料形成在开口之间的开口和半导体材料的开口之间的区域上。 绝缘材料沿着每个开口的中心形成并完全通过栅极材料形成。 栅极材料的一段从一个开口延伸到另一个，并且在开口之间缠绕半导体材料的柱。 该段是晶体管的栅极。 源极/漏极区域形成在栅极的相对侧上。

公开(公告)号：US09076686B1

公开(公告)日：2015-07-07

申请号：US14152664

申请日：2014-01-10

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66666

Abstract: A field effect transistor construction comprises two source/drain regions and a channel region there-between. The channel region comprises a transition metal dichalcogenide material having a thickness of 1 monolayer to 7 monolayers and having a physical length between the source/drain regions. A mid-gate is operatively proximate a mid-portion of the channel region relative to the physical length. A pair of gates is operatively proximate different respective portions of the channel region from the portion of the channel region that the mid-gate is proximate. The pair of gates are spaced and electrically isolated from the mid-gate on opposite sides of the mid-gate. Gate dielectric is between a) the channel region, and b) the mid-gate and the pair of gates. Additional embodiments are disclosed.

Abstract translation: 场效应晶体管结构包括两个源极/漏极区域和其间的沟道区域。 通道区域包含厚度为1单层至7层的过渡金属二硫属元素材料，并且在源极/漏极区域之间具有物理长度。 中间栅极相对于物理长度可操作地邻近沟道区的中部。 一对门可操作地接近沟道区域与中栅极接近的沟道区域的部分的不同相应部分。 一对门与中门对面的中间门隔开并与之隔离。 栅极电介质位于a）沟道区域之间，b）中间栅极与栅极对之间。 公开了另外的实施例。