公开(公告)号：US06864583B2

公开(公告)日：2005-03-08

申请号：US10401791

申请日：2003-03-31

申请人： Noriaki Matsunaga ,  Takamasa Usui ,  Sachiyo Ito

发明人： Noriaki Matsunaga ,  Takamasa Usui ,  Sachiyo Ito

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

摘要： A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

摘要翻译： 布线层由第一有机SOG层，由氧化硅膜或由等离子体CVD法形成的氮化硅膜构成的加强绝缘层和第二有机SOG层覆盖。 在第一有机SOG层和加强绝缘层中形成通孔，并且在第二有机SOG层中形成与通孔对应的沟槽。 导电通孔塞和电极垫分别嵌入通孔和沟槽中。 第二SOG层被钝化层覆盖，其中形成通孔以露出电极焊盘。 导线连接到通孔中暴露的电极焊盘。

公开(公告)号：US06670712B2

公开(公告)日：2003-12-30

申请号：US10286752

申请日：2002-11-04

申请人： Noriaki Matsunaga

发明人： Noriaki Matsunaga

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L22/34 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  Y10T29/49155 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device of the present invention comprises a first split Pad electrode which is electrically connected to wirings and a MOSFET and a second split Pad electrode which is not electrically connected to wirings and a MOSFET. Then, a passivation film which covers a part of the surface of the second split pad electrode is formed and a non-split pad electrode which covers the surfaces of the first and second split pad electrodes which are not covered with the passivation film is formed.

摘要翻译： 本发明的半导体器件包括电连接到布线的第一分离焊盘电极和MOSFET，以及不与布线电连接的MOSFET和第二分离焊盘电极。 然后，形成覆盖第二分割焊盘电极表面的一部分的钝化膜，并且形成覆盖未被钝化膜覆盖的第一和第二分离焊盘电极的表面的非分裂焊盘电极。

公开(公告)号：US06563218B2

公开(公告)日：2003-05-13

申请号：US09995602

申请日：2001-11-29

申请人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

发明人： Noriaki Matsunaga ,  Yoshiaki Shimooka ,  Kazuyuki Higashi ,  Hideki Shibata

IPC分类号： H01L2348

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/05556 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

摘要翻译： 多个布线层层压在LSI芯片上。 每个布线层包括施加有机械压力的电极，形成在需要具有高机械强度且其中形成有电极的区域中的第一绝缘膜，形成在与第一绝缘膜相同的层中的第二绝缘膜 形成在不需要比第一绝缘层高的机械强度的区域中的第一绝缘膜的层，以及形成在第二绝缘膜的表面上的布线层。

公开(公告)号：US06534870B1

公开(公告)日：2003-03-18

申请号：US09594843

申请日：2000-06-15

申请人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata ,  Rempei Nakata ,  Hideshi Miyajima ,  Motonobu Kawai

发明人： Yoshiaki Shimooka ,  Noriaki Matsunaga ,  Hideki Shibata ,  Rempei Nakata ,  Hideshi Miyajima ,  Motonobu Kawai

IPC分类号： H01L23485

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Al wirings of first to fifth layers are formed on a P—SiO2 film, and FSG films are formed between the wiring layers. An organic silicon oxide film is formed between wirings in one same wiring layer. The Al wirings in the first and second layers have a carbon concentration of 22 wt %, and the Al wirings in the third to fifth layers have a carbon concentration of 20 wt %.

摘要翻译： 在P-SiO 2膜上形成第一至第五层的Al布线，并且在布线层之间形成FSG膜。 在一个相同的布线层中的布线之间形成有机氧化硅膜。 第一层和第二层的Al配线的碳浓度为22重量％，第三至第五层的Al配线的碳浓度为20重量％。

公开(公告)号：US06368951B2

公开(公告)日：2002-04-09

申请号：US09903992

申请日：2001-07-13

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L214763

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US06342444B1

公开(公告)日：2002-01-29

申请号：US09522595

申请日：2000-03-10

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Hiroshi Toyoda ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.

摘要翻译： 通过在绝缘膜上选择性地形成Si金属层作为蚀刻掩模的以下步骤之后，通过选择性地除去Si金属层上的Ti金属层，在Cu金属层上选择性地形成TiN膜作为阻挡层，形成 沟槽图案，通过使用Si金属层选择性去除绝缘膜，在沟槽图案中形成具有Si金属层的Cu金属层，在Si金属层上形成Ti金属层，将Cu金属层形成为阻挡材料 在氮气气氛中通过热处理与与蚀刻掩模的反应与Cu的不同种类的共晶反应，并且通过在气氛中热处理Ti金属层来选择性地氮化Cu金属层上的Ti金属层 的氮气。

公开(公告)号：US08758841B2

公开(公告)日：2014-06-24

申请号：US10510497

申请日：2003-04-11

申请人： Shunji Hayashi ,  Shigeru Aizawa ,  Naoki Taketomo ,  Tadashi Nakatsubo ,  Noriaki Matsunaga ,  Katsunori Kimura

发明人： Shunji Hayashi ,  Shigeru Aizawa ,  Naoki Taketomo ,  Tadashi Nakatsubo ,  Noriaki Matsunaga ,  Katsunori Kimura

IPC分类号： A23C9/12

CPC分类号： A23C19/0323 ,  A23Y2220/37

摘要： Natural cheese which comprises a lactic acid bacterium belonging to Lactobacillus gasseri having a disinfection potency against Helicobacter pylori, and a method for producing the natural cheese.

摘要翻译： 天然乳酪，其含有具有对幽门螺杆菌的消毒效力的属于加氏乳杆菌的乳酸菌，以及天然干酪的制造方法。

公开(公告)号：US07996813B2

公开(公告)日：2011-08-09

申请号：US12654865

申请日：2010-01-07

申请人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

发明人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

IPC分类号： G06F15/04

CPC分类号： G06F17/5068

摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

公开(公告)号：US20110006425A1

公开(公告)日：2011-01-13

申请号：US12726520

申请日：2010-03-18

申请人： Makoto Wada ,  Noriaki Matsunaga ,  Yosuke Akimoto

发明人： Makoto Wada ,  Noriaki Matsunaga ,  Yosuke Akimoto

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer.

摘要翻译： 根据一个实施例的半导体器件包括：半导体衬底; 绝缘膜，设置在所述半导体基板上并且包含布线沟槽; 第一催化剂层，直接地或经由布线沟槽的侧表面和底表面上的另一个构件提供; 以及设置在所述布线沟槽中以沿着所述布线沟槽的侧面和底面的第一石墨烯层，所述第一石墨烯层设置在所述第一催化剂层上以与所述第一催化剂层接触。

公开(公告)号：US20100237501A1

公开(公告)日：2010-09-23

申请号：US12726604

申请日：2010-03-18

申请人： Hideyuki Tomizawa ,  Noriaki Matsunaga ,  Tadayoshi Watanabe ,  Shiro Mishima ,  Masako Kodera

发明人： Hideyuki Tomizawa ,  Noriaki Matsunaga ,  Tadayoshi Watanabe ,  Shiro Mishima ,  Masako Kodera

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76826 ,  H01L21/3105 ,  H01L21/76832 ,  H01L21/76849 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成包括硅，氧，碳和氢的绝缘膜，在绝缘膜中形成布线沟槽，在绝缘膜上形成金属膜作为金属布线，使得 金属膜设置在布线沟槽中，通过去除布线沟槽外的金属膜形成金属布线，在形成金属布线之后对绝缘膜的表面进行疏水处理，并在上部选择性地形成金属帽 在执行疏水处理之后通过电镀的金属布线的表面。