公开(公告)号：US11374118B2

公开(公告)日：2022-06-28

申请号：US16936352

申请日：2020-07-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/268 ,  H01L27/088

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

公开(公告)号：US20220147689A1

公开(公告)日：2022-05-12

申请号：US17581884

申请日：2022-01-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: A method of designing a 3D Integrated Circuit, including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer includes a Computer Aided Design tool, where the 3D Integrated Circuit includes a plurality of connections between the logic and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit connected so to write data to the first memory array, where the first placement includes placement of the first memory array, and where the second placement includes placement of the first logic circuit based on the placement of the first memory array.

公开(公告)号：US20190237461A1

公开(公告)日：2019-08-01

申请号：US16242300

申请日：2019-01-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H01L29/812 ,  H01L29/808 ,  H01L27/092 ,  H01L29/732 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/786 ,  H01L29/45 ,  H01L29/423 ,  H01L23/367 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/02 ,  H01L23/544 ,  H01L23/48 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  G03F9/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

Abstract: A 3D semiconductor device including: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.

公开(公告)号：US20180350686A1

公开(公告)日：2018-12-06

申请号：US16043133

申请日：2018-07-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/8221 ,  G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  G11C29/82 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796

Abstract: A 3D semiconductor device, the device including: a substrate including a single crystal layer; a plurality of first transistors in and on the single crystal layer; at least one metal layer, where the at least one metal layer overlays the plurality of first transistors and the at least one metal layer includes connections between the first transistors, and where a portion of the connections between the first transistors form memory peripheral circuits; a stack of at least sixteen layers, where the stack of sixteen layers includes odd numbered layers and even numbered layers of a different composition and overlays the at least one metal layer, a multilevel memory structure, where the multilevel memory structure includes the stack of at least sixteen layers, where the stack of at least sixteen layers includes at least eight layers of memory cells controlled by the memory peripheral circuits.

公开(公告)号：US10002865B2

公开(公告)日：2018-06-19

申请号：US15482761

申请日：2017-04-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H03K19/096 ,  H01L23/34 ,  H01L23/50 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L27/0688 ,  G11C11/401 ,  G11C29/006 ,  G11C29/76 ,  H01L22/22 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5252 ,  H01L23/5286 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099

Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines, where the second stratum includes a first layer including first transistors and a second layer including second transistors, where the first layer includes a first bus, the first bus interconnecting a plurality of first logic units, where the second layer includes a second bus, the second bus interconnecting a plurality of second logic units.

公开(公告)号：US20170301667A1

公开(公告)日：2017-10-19

申请号：US15482761

申请日：2017-04-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H01L23/34 ,  H03K19/096 ,  H01L23/48 ,  H01L23/50 ,  H01L23/525

CPC classification number: H01L27/0688 ,  G01R31/3187 ,  G01R31/31937 ,  G11C11/401 ,  G11C29/006 ,  G11C29/76 ,  H01L22/22 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5252 ,  H01L23/5286 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099

Abstract: A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first stratum includes an array of memory cells including at least four rows of memory cells, each of the rows is controlled by a bit-line, where the array of memory cells includes a plurality of columns of memory cells, each of the columns is controlled by a word-line, and where the second stratum includes memory control circuits directly connected to the bit-lines and the word-lines.

公开(公告)号：US20170162585A1

公开(公告)日：2017-06-08

申请号：US15222832

申请日：2016-07-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/112 ,  H01L23/525

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.

公开(公告)号：US09142553B2

公开(公告)日：2015-09-22

申请号：US14628231

申请日：2015-02-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H01L27/06 ,  H03K19/096 ,  H01L23/34 ,  H01L23/48 ,  H01L23/50

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure and a second clock origin, where the second clock origin is connected to the first clock distribution structure with a plurality of through layer vias, and where the second layer thickness is less than 1 micrometer.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分布结构，其中第二层包括第二时钟分布结构和第二时钟源，其中第二时钟源为 连接到具有多个通过层通孔的第一时钟分配结构，并且其中第二层厚度小于1微米。

公开(公告)号：US20240403533A1

公开(公告)日：2024-12-05

申请号：US18800058

申请日：2024-08-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.

公开(公告)号：US20210357568A1

公开(公告)日：2021-11-18

申请号：US17385082

申请日：2021-07-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, and the second placement includes placement of the first logic circuit based on the placement of the first memory array.