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178 条记录 (耗时 0.034 秒)

    Memory cell leakage reduction
    41.
    发明授权
    Memory cell leakage reduction 有权
    存储单元泄漏减少

    公开(公告)号：US06724649B1

    公开(公告)日：2004-04-20

    申请号：US10324178

    申请日：2002-12-19

    申请人： Yibin Ye ,  Dinesh Somasekhar ,  Vivek K. De

    发明人： Yibin Ye ,  Dinesh Somasekhar ,  Vivek K. De

    IPC分类号： G11C1100

    CPC分类号： G11C11/418

    摘要： Leakage current from non-selected memory cells is substantially eliminated by placing a negative voltage on the selection line of the non-selected cells. This negative voltage on the gate of the access transistors in the cells reduces the leakage current that would otherwise leak onto a shared sense line if the selection line were biased at 0 volts. In one embodiment the pre-charge voltage on the affected sense line is reduced so that the difference between the pre-charge voltage and the negative voltage does not exceed the design voltage of the transistors in the memory cells.

    摘要翻译： 通过在非选择的单元的选择线上放置负电压，基本上消除了来自非选择存储单元的泄漏电流。 如果选择线偏置在0伏特，则单元中的存取晶体管的栅极上的负电压减小了否则将泄漏到共享检测线上的漏电流。 在一个实施例中，受影响的感测线上的预充电电压减小，使得预充电电压和负电压之间的差不超过存储器单元中的晶体管的设计电压。

    SRAM array with dynamic voltage for reducing active leakage power
    42.
    发明授权
    SRAM array with dynamic voltage for reducing active leakage power 有权
    具有动态电压的SRAM阵列，用于降低有源漏电功率

    公开(公告)号：US06724648B2

    公开(公告)日：2004-04-20

    申请号：US10117163

    申请日：2002-04-05

    申请人： Muhammad Khellah ,  Vivek De ,  Dinesh Somasekhar ,  Yibin Ye

    发明人： Muhammad Khellah ,  Vivek De ,  Dinesh Somasekhar ,  Yibin Ye

    IPC分类号： G11C1140

    CPC分类号： G11C11/417

    摘要： A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.

    摘要翻译： 具有动态电源电压的电源管理器件和静态随机存取存储器（SRAM）架构降低了SRAM单元中的有功功率泄漏。 当单元不活动时，低电平电源电压被施加到连接到单元的源极线以维持存储在单元中的数据。 然而，在单元被访问之前（例如，在读取或写入操作期间），源极线被升高到高电平电源电压。

    Flip flop circuit
    43.
    发明授权
    Flip flop circuit 失效
    触发电路

    公开(公告)号：US06459316B1

    公开(公告)日：2002-10-01

    申请号：US09733216

    申请日：2000-12-08

    申请人： Sriram R. Vangal ,  Dinesh Somasekhar

    发明人： Sriram R. Vangal ,  Dinesh Somasekhar

    IPC分类号： H03K3289

    CPC分类号： H03K3/0372 ,  H03K3/356121

    摘要： A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

    摘要翻译： 具有互补输出的双轨触发器包括具有嵌入式逻辑的主级，感测级和一个或多个从动级。 触发器工作在预充电状态和评估状态。 在时钟信号为低电平的预充电状态期间，触发器将内部保持器节点预充电到高电平。 当时钟信号变为高电平时，触发器进入评估状态，并且内部保持器节点之一评估为低值。 感觉阶段感知内部维护者节点评估为零，并将其驱动到零更快。 从站阶段在评估状态期间反映内部守门员节点的状态，并在预充电状态期间维持其状态。

    Differential current switch logic gate
    44.
    发明授权
    Differential current switch logic gate 失效
    差分电流开关逻辑门

    公开(公告)号：US6014041A

    公开(公告)日：2000-01-11

    申请号：US937832

    申请日：1997-09-26

    申请人： Dinesh Somasekhar ,  Kaushik Roy ,  Junji Sugisawa

    发明人： Dinesh Somasekhar ,  Kaushik Roy ,  Junji Sugisawa

    IPC分类号： H03K3/356 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H03K3/356165 ,  H03K3/356113

    摘要： A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

    摘要翻译： 提供了具有包括多个输入端子和一对互补输出节点的评估树的差分电流开关逻辑（DCSL）系统。 DCSL系统还具有输出网络，其在预充电阶段期间以预定电平建立一对状态输出，并且在评估阶段期间响应于评估树输出节点建立互补电平的状态输出。 第一和第二NMOS晶体管串联连接在DCVS输出状态网络和评估树输出节点之间，其门耦合到状态输出，以将评估树的输出与评估树隔离。

    Increasing the surface area of a memory cell capacitor
    47.
    发明授权
    Increasing the surface area of a memory cell capacitor 有权
    增加存储单元电容器的表面积

    公开(公告)号：US08232588B2

    公开(公告)日：2012-07-31

    申请号：US12749389

    申请日：2010-03-29

    申请人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    发明人： Brian S. Doyle ,  Robert S. Chau ,  Vivek De ,  Suman Datta ,  Dinesh Somasekhar

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

    摘要翻译： 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 在第三绝缘层上沉积第二导电层。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。