公开(公告)号：US20160133722A1

公开(公告)日：2016-05-12

申请号：US15000127

申请日：2016-01-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L29/66651 ,  H01L21/28035 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

公开(公告)号：US20160071795A1

公开(公告)日：2016-03-10

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160005822A1

公开(公告)日：2016-01-07

申请号：US14321568

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Kern RIM ,  Zhongze WANG

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer.

Abstract translation: 系统和方法涉及三端子半导体器件，其包括用于连接到栅极端子的自对准通孔。硬掩模和形成在到漏极端子的漏极连接的顶部和侧壁部分上的间隔物以及到源极端子的源极连接 保护和绝缘漏极连接和源极连接，从而避免在源极和漏极连接和自对准通孔之间产生短路。 自对准通孔在栅极端子和诸如M1金属线的金属线之间提供直接的金属栅极连接路径，同时避免了单独的栅极连接层。

公开(公告)号：US20150235948A1

公开(公告)日：2015-08-20

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Ohsang KWON ,  Kern RIM ,  John Jianhong ZHU ,  Xiangdong CHEN ,  Foua VANG ,  Raymond George STEPHANY ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20150194525A1

公开(公告)日：2015-07-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US20190157160A1

公开(公告)日：2019-05-23

申请号：US15817452

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Cimang LU ,  Stanley Seungchul SONG ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308

Abstract: Aspects of the disclosure are directed to a semiconductor device. The semiconductor device may include a plurality of fins formed on a semiconductor substrate including a bulk semiconductor material, a plurality of shallow trench isolation (STI) trenches formed between the plurality of fins, a hardmask formed around the plurality of fins, and a plurality of fin bottom portions formed below the plurality of fins.

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。

公开(公告)号：US20160370699A1

公开(公告)日：2016-12-22

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Hyeokjin Bruce LIM ,  Ohsang KWON ,  Mickael MALABRY ,  Jingwei ZHANG ,  Raymond George STEPHANY ,  Haining YANG ,  Kern RIM ,  Stanley Seungchul SONG ,  Mukul GUPTA ,  Foua VANG

IPC: G03F1/70 ,  G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5068

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract translation: 在本公开的一个方面，提供了一种方法，计算机可读介质和用于分配多个图案化处理的特征颜色的装置。 该装置接收集成电路布局信息，该信息包括一组特征的集合，以及针对特征集合的第一特征集的每个特征的多种颜色的分配颜色。 另外，该装置对特征的第二子集执行颜色分解，以将颜色分配给第二特征子集中的特征。 特征的第二子集包括不包括在具有分配颜色的特征的第一子集中的特征集合中的特征。

公开(公告)号：US20160240437A1

公开(公告)日：2016-08-18

申请号：US15141198

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20160093364A1

公开(公告)日：2016-03-31

申请号：US14499147

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Younghwi YANG ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation.

Abstract translation: 系统和方法包括具有存取晶体管的静态随机存取存储器（SRAM）位单元电路，存取晶体管被配置为将读取电流传递到存储节点，存取晶体管包括存取晶体管背栅极。 存取晶体管背栅极被偏置以使得在读取操作期间读取电流的选择性电流升高。