公开(公告)号：US20220147472A1

公开(公告)日：2022-05-12

申请号：US17534180

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US10811062B2

公开(公告)日：2020-10-20

申请号：US16528523

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20200293469A1

公开(公告)日：2020-09-17

申请号：US16828570

申请日：2020-03-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/3234

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

公开(公告)号：US10593379B2

公开(公告)日：2020-03-17

申请号：US16109607

申请日：2018-08-22

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20190392875A1

公开(公告)日：2019-12-26

申请号：US16459330

申请日：2019-07-01

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G11C7/02 ,  G06F13/16

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US20190196992A1

公开(公告)日：2019-06-27

申请号：US16228695

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US10270442B2

公开(公告)日：2019-04-23

申请号：US16051291

申请日：2018-07-31

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F3/06 ,  G11C16/06 ,  G11C11/417 ,  G11C16/32 ,  G11C11/413 ,  G11C11/4063 ,  G11C11/401 ,  G11C11/41 ,  G11C16/26 ,  G11C11/419 ,  H03K19/0175 ,  G11C11/4093 ,  G06F13/40

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

公开(公告)号：US10062421B2

公开(公告)日：2018-08-28

申请号：US15626097

申请日：2017-06-17

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20160343417A1

公开(公告)日：2016-11-24

申请号：US15160538

申请日：2016-05-20

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C7/10 ,  G06F1/08

CPC classification number: G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

Abstract translation: 在说明性实施例中，存储器电路包括用于读和写存储器操作的数据被传送的第一和第二数据路径，以及用于调整施加到其输入的时钟信号的相位的第一和第二混频器电路。 混频器电路交叉耦合，使得第一和第二混频器的输出都可用于第一和第二数据路径。 一个混频器用于提供第一相位调整的时钟信号供操作电路使用，另一个混频器用于提供第二相位调整的时钟信号，供随后的操作使用。

公开(公告)号：US20160005489A1

公开(公告)日：2016-01-07

申请号：US14857794

申请日：2015-09-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: G11C16/32 ,  G11C16/26

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.

Abstract translation: IC芯片经由时间复用的外部信号线在各自的时间将命令信号，地址信号和数据信号发送到闪速存储器件，数据信号表示要存储在闪速存储器的非易失性存储元件阵列内的数据 设备。 IC芯片还经由一个或多个外部控制信号线将控制信号发送到闪速存储器件，该控制信号指示闪速存储器件可切换地将片上端接元件耦合到时分多路信号线。