公开(公告)号：US20170033226A1

公开(公告)日：2017-02-02

申请号：US15217080

申请日：2016-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Motomu KURATA ,  Yuta ENDO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/8258 ,  H01L22/12 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

Abstract translation: 提供一种包括具有小型化结构的晶体管的半导体器件。 第一绝缘体设置在堆叠中，其中半导体，第一导体和第二导体以该顺序堆叠。 在第一绝缘体上形成蚀刻掩模。 使用蚀刻掩模，蚀刻第一绝缘体和第二导体，直到暴露出第一导体。 在蚀刻第一导体直到半导体暴露以形成宽度小于第二导体的沟槽之后，依次形成第二绝缘体和第三导体。

公开(公告)号：US20160300933A1

公开(公告)日：2016-10-13

申请号：US15190677

申请日：2016-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US20160284739A1

公开(公告)日：2016-09-29

申请号：US15180642

申请日：2016-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/465 ,  H01L29/66

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

公开(公告)号：US20160099259A1

公开(公告)日：2016-04-07

申请号：US14870912

申请日：2015-09-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Tomoaki MORIWAKA ,  Shinya SASAGAWA ,  Takashi OHTSUKI

IPC: H01L27/12 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/1255 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

Abstract translation: 提供具有低功耗的小型化半导体器件。 制造布线层的方法包括以下步骤：在第一绝缘体上形成第二绝缘体; 在所述第二绝缘体上形成第三绝缘体; 在第三绝缘体中形成开口，使其到达第二绝缘体; 在第三绝缘体和开口中形成第一导体; 在所述第一导体上形成第二导体; 并且在形成第二导体之后，进行抛光处理以去除第三绝缘体的顶表面上方的第一和第二导体的部分。 第一导体的端部处于低于或等于开口顶部水平的水平。 第二导体的顶表面处于低于或等于第一导体末端的水平面。

公开(公告)号：US20160093642A1

公开(公告)日：2016-03-31

申请号：US14961061

申请日：2015-12-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L27/12 ,  H01L27/115 ,  H01L29/417 ,  H01L29/10 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

公开(公告)号：US20150236166A1

公开(公告)日：2015-08-20

申请号：US14700528

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Tetsuhiro TANAKA ,  Junichi KOEZUKA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

Abstract translation: 提供了一种具有稳定和高电特性并且高产率的小型化晶体管。 在包括依次层叠有氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管的半导体装置中，设置与栅电极层的侧面接触的第一侧壁绝缘层， 提供第二侧壁绝缘层以覆盖第一侧壁绝缘层的侧表面。 第一侧壁绝缘层是在其侧表面上形成具有均匀形状的缝隙的氧化铝膜。 第二侧壁绝缘层设置成覆盖缝隙。 源电极层和漏电极层设置成与氧化物半导体膜和第二侧壁绝缘层接触。

公开(公告)号：US20150214381A1

公开(公告)日：2015-07-30

申请号：US14680191

申请日：2015-04-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/247 ,  H01L29/263 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/78693 ,  H01L29/78696

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

公开(公告)号：US20150214041A1

公开(公告)日：2015-07-30

申请号：US14678134

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Shinya SASAGAWA

IPC: H01L21/02

CPC classification number: H01L21/02244 ,  H01L21/02107 ,  H01L21/02252 ,  H01L21/02323 ,  H01L21/02521 ,  H01L27/1156 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: In a processing method of a stacked-layer film in which a metal film is provided on an oxide insulating film, plasma containing an oxygen ion is generated by applying high-frequency power with power density greater than or equal to 0.59 W/cm2 and less than or equal to 1.18 W/cm2 to the stacked-layer film side under an atmosphere containing oxygen in which pressure is greater than or equal to 5 Pa and less than or equal to 15 Pa, the metal film is oxidized by the oxygen ion, and an oxide insulating film containing excess oxygen is formed by supplying oxygen to the oxide insulating film.

Abstract translation: 在氧化物绝缘膜上设置有金属膜的叠层膜的处理方法中，通过施加功率密度大于等于0.59W / cm 2的高频电力产生含有氧离子的等离子体 在含有大于或等于5Pa且小于或等于15Pa的氧的气氛下，叠层层一侧的厚度为1.18W / cm 2以下，金属膜被氧离子氧化， 并且通过向氧化物绝缘膜供给氧而形成含有过量氧的氧化物绝缘膜。

公开(公告)号：US20140179058A1

公开(公告)日：2014-06-26

申请号：US14191853

申请日：2014-02-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Shunichi ITO ,  Miyuki HOSOBA

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/78621 ,  H01L29/7869

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract translation: 本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中 倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个 强度 在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

公开(公告)号：US20140103337A1

公开(公告)日：2014-04-17

申请号：US14054078

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L21/02 ,  H01L29/26 ,  H01L29/78

CPC classification number: H01L21/02565 ,  H01L21/02617 ,  H01L21/02631 ,  H01L27/1156 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.

Abstract translation: 通过抑制其电特性的变化来提供包括氧化物半导体的高度可靠的半导体器件。 氧气由设置在氧化物半导体层下方的基底绝缘层和设置在氧化物半导体层上的栅极绝缘层提供到形成沟道的区域，从而填充可能在沟道中产生的氧空位。 此外，通过在氧化物半导体层中形成的沟道附近的源极电极层或漏极电极层从氧化物半导体层提取氧被抑制，由此抑制在沟道中可能产生的氧空位。