公开(公告)号：US10354926B2

公开(公告)日：2019-07-16

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L23/522 ,  H01L29/06

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US09876122B2

公开(公告)日：2018-01-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20160336070A1

公开(公告)日：2016-11-17

申请号：US14980853

申请日：2015-12-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/08 ,  G11C16/26 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

Abstract translation: 包括存储器单元的行和列的非易失性存储器，存储器单元的列包括包括公共选择门的双存储单元对。 根据本公开，每列存储器单元提供两个位线。 相同列的相邻双存储单元不连接到相同的位线，同一列的相邻非双存储单元连接到相同的位线。

公开(公告)号：US09368215B2

公开(公告)日：2016-06-14

申请号：US14810283

申请日：2015-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.

Abstract translation: 一种方法控制包括形成在半导体衬底中的双存储单元的存储器。 每个存储单元包括一个浮动栅极晶体管，它包括状态控制栅极，与选择晶体管串联，该选择​​晶体管包括双存储单元共用的垂直选择控制栅极和连接到存储器共用的嵌入式源极线路的源极 细胞。 双存储单元的浮栅晶体管的漏极连接到相同的位线。 该方法包括在编程或读取另一个存储器单元的步骤期间控制存储器单元以将其导通以将源极线耦合到耦合到地的位线。

公开(公告)号：US20150348640A1

公开(公告)日：2015-12-03

申请号：US14724229

申请日：2015-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/26 ,  H01L21/28 ,  H01L27/115 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。

公开(公告)号：US20150325581A1

公开(公告)日：2015-11-12

申请号：US14806432

申请日：2015-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Abstract translation: 集成电路形成在半导体衬底上，并且包括沟槽导体和形成在衬底表面上的第一晶体管。 晶体管包括：晶体管栅极结构，在栅极结构的第一边缘和沟槽导体的上边缘之间的衬底中延伸的第一掺杂区域和形成在栅极结构的第一边缘上方的第一间隔区， 第一掺杂区域。 第一间隔物完全覆盖第一掺杂区域，并且硅化物存在于沟槽导体上，但不存在于第一掺杂区域的表面上。

公开(公告)号：US09076878B2

公开(公告)日：2015-07-07

申请号：US14043718

申请日：2013-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/115 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。

公开(公告)号：US08830761B2

公开(公告)日：2014-09-09

申请号：US13786202

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C11/56 ,  G11C8/12

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US11139303B2

公开(公告)日：2021-10-05

申请号：US17026869

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20200274722A1

公开(公告)日：2020-08-27

申请号：US16783631

申请日：2020-02-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: H04L9/32 ,  G06F21/72 ,  G06F21/60 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.