利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

196 条记录 (耗时 0.029 秒)

    Integrated circuits and methods of forming a field effect transistor
    42.
    发明授权
    Integrated circuits and methods of forming a field effect transistor 有权
    集成电路和形成场效应晶体管的方法

    公开(公告)号：US07244659B2

    公开(公告)日：2007-07-17

    申请号：US11076774

    申请日：2005-03-10

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L21/76

    CPC分类号： H01L29/0653 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

    摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

    摘要翻译： 公开了形成场效应晶体管的集成电路和方法。 在一个方面，集成电路包括包括本体半导体材料的半导体衬底。 电绝缘材料容纳在本体半导体材料内。 在绝缘材料上形成半导体材料。 包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。 在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。 在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。 公开了其他方面和实施方式，包括方法方面。

    Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers
    44.
    发明授权
    Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers 有权
    在包括具有间隔物的T形沟槽的半导体衬底内形成沟槽隔离的方法

    公开(公告)号：US06727150B2

    公开(公告)日：2004-04-27

    申请号：US10206171

    申请日：2002-07-26

    申请人： Sanh D. Tang

    发明人： Sanh D. Tang

    IPC分类号： H01L21336

    CPC分类号： H01L21/823481 ,  H01L21/76229

    摘要： A method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench. Other aspects and implementations are contemplated.

    摘要翻译： 在半导体衬底内形成沟槽隔离的方法包括在半导体衬底内形成第一开口尺寸的第一隔离沟槽。 第一隔离槽具有基座。 第二隔离沟槽通过第一隔离沟槽的基底形成到半导体衬底中。 第二隔离沟槽沿着与第一开放尺寸平行的线具有小于第一开放尺寸的第二开口尺寸。 绝缘隔离材料形成在第一和第二隔离沟槽内。 绝缘隔离材料具有从第二隔离沟槽内延伸到第一隔离沟槽的空隙。 考虑了其他方面和实现。

    Local interconnect structures for integrated circuits and methods for making the same
    45.
    发明授权
    Local interconnect structures for integrated circuits and methods for making the same 失效
    用于集成电路的局部互连结构及其制造方法

    公开(公告)号：US06693025B2

    公开(公告)日：2004-02-17

    申请号：US09943994

    申请日：2001-08-30

    申请人： Sanh D. Tang ,  Michael P. Violette

    发明人： Sanh D. Tang ,  Michael P. Violette

    IPC分类号： H01L2128

    CPC分类号： G01R31/3648 ,  G01R31/3665 ,  H01L21/76895 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for making a flexible metal silicide local interconnect structure. The method includes forming an amorphous or polycrystalline silicon layer on a substrate including at least one gate structure, forming a layer of silicon nitride over the silicon layer, removing a portion of the silicon nitride layer, oxidizing the exposed portion of the silicon layer, removing the remaining portion of the silicon nitride layer, optionally removing the oxidized silicon layer, forming a metal layer over the resulting structure, annealing the metal layer in an atmosphere comprising nitrogen, and removing any metal nitride regions. The local metal silicide interconnect structure may overlie the at least one gate structure. The methods better protect underlying silicon regions (e.g., substrate), as well as form TiSix local interconnects with good step coverage. Intermediate and resulting structures are also disclosed.

    摘要翻译： 一种制造柔性金属硅化物局部互连结构的方法。 该方法包括在包括至少一个栅极结构的衬底上形成非晶或多晶硅层，在硅层上形成氮化硅层，去除氮化硅层的一部分，氧化硅层的暴露部分，去除 氮化硅层的剩余部分，任选地去除氧化硅层，在所得结构上形成金属层，在包含氮的气氛中退火金属层，并去除任何金属氮化物区域。 局部金属硅化物互连结构可以覆盖至少一个栅极结构。 这些方法更好地保护底层硅区域（例如底层），以及形成具有良好阶梯覆盖的TiSix局部互连。 还公开了中间和结构的结构。

    Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench
    46.
    发明授权
    Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench 失效
    通过从沟槽部分去除导电材料在多层互连结构中形成插塞的方法

    公开(公告)号：US06352916B1

    公开(公告)日：2002-03-05

    申请号：US09432516

    申请日：1999-11-02

    申请人： Sanh D. Tang ,  Rajendra Narasimhan

    发明人： Sanh D. Tang ,  Rajendra Narasimhan

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.

    摘要翻译： 在半导体器件中，提供了包括互连的导电结构和从其整体延伸的上覆插塞。 该结构可以通过镶嵌工艺来提供，其中开口被限定在绝缘层中足够深以适应互连件及其上覆塞子的高度。 开口填充有金属，然后金属的非插塞区域向下凹陷到沟槽内的标准互连高度。 金属的全高度保留在插塞位置。 然后将氧化物沉积在凹陷部分上。 或者，提供足够深的连续金属层以适应互连件及其上覆插头的高度。 然后蚀刻金属以形成互连/插塞结构，并在其上沉积绝缘体。 可以使用这些过程在同一级别提供多个结构，并且可以类似地提供这些结构的多个级别。

    Dual poly integrated circuit interconnect
    47.
    发明授权
    Dual poly integrated circuit interconnect 有权
    双聚合集成电路互连

    公开(公告)号：US5923584A

    公开(公告)日：1999-07-13

    申请号：US134005

    申请日：1998-08-14

    申请人： Martin C. Roberts ,  Sanh D. Tang

    发明人： Martin C. Roberts ,  Sanh D. Tang

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  G11C13/00 ,  G11C11/40

    CPC分类号： H01L27/10882 ,  H01L21/76838 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002

    摘要： An electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

    摘要翻译： 覆盖衬底的掩埋接触区域的电互连的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。 通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。 去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。 然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。