公开(公告)号：US07132323B2

公开(公告)日：2006-11-07

申请号：US10713447

申请日：2003-11-14

申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US07067886B2

公开(公告)日：2006-06-27

申请号：US10605888

申请日：2003-11-04

申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

IPC分类号： H01L23/62

CPC分类号： H01L27/0251

摘要： A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

摘要翻译： 一种方法和结构改变具有硅绝缘体（SOI）晶体管的集成电路设计。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 跟踪电网），并且在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

公开(公告)号：US06956417B2

公开(公告)日：2005-10-18

申请号：US10707123

申请日：2003-11-21

申请人： Kerry Bernstein ,  Anthony R. Bonaccio ,  John A. Fifield ,  Allen P. Haar ,  Shiu C. Ho ,  Terence B. Hook ,  Michael A. Soma ,  Stephen D. Wyatt

发明人： Kerry Bernstein ,  Anthony R. Bonaccio ,  John A. Fifield ,  Allen P. Haar ,  Shiu C. Ho ,  Terence B. Hook ,  Michael A. Soma ,  Stephen D. Wyatt

IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/0891

摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.

摘要翻译： 一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

公开(公告)号：US06825490B1

公开(公告)日：2004-11-30

申请号：US10605567

申请日：2003-10-09

申请人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

发明人： Terence B. Hook ,  Raminderpal Singh ,  Stephen D. Wyatt

IPC分类号： H01L2358

CPC分类号： G01R35/005

摘要： A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.

摘要翻译： 确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。 半导体器件包括电容器，校准电阻器和校准电路。 施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。 校准电路适于测量对电容器充电所需的实际时间。 校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。

公开(公告)号：US06489223B1

公开(公告)日：2002-12-03

申请号：US09898949

申请日：2001-07-03

申请人： Terence B. Hook ,  Randy W. Mann

发明人： Terence B. Hook ,  Randy W. Mann

IPC分类号： H01L21425

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66659 ,  H01L29/7835

摘要： Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the structure. Other structures have no barrier or have two barriers. Source and drain engineering can be performed for LDD, halo, and other desired implants.

摘要翻译： 不同的对称和非对称装置在同一芯片上使用非关键块掩模和成角度的植入物形成。 选择性地在结构的一侧形成势垒，并且该势垒阻挡以一定角度朝向该结构注入的掺杂剂。 其他结构没有障碍或有两个障碍。 可以对LDD，光晕和其他所需的植入物进行源和漏极工程。

公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06256755B1

公开(公告)日：2001-07-03

申请号：US09174789

申请日：1998-10-19

申请人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

发明人： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

IPC分类号： G11C2900

CPC分类号： G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

摘要： An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

摘要翻译： 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

公开(公告)号：US5972765A

公开(公告)日：1999-10-26

申请号：US895049

申请日：1997-07-16

申请人： William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

发明人： William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336

CPC分类号： H01L21/28211 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/665 ,  H01L29/66575

摘要： Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

摘要翻译： 形成半导体器件的膜的方法，其中在形成膜期间提供包含氘化物质的源材料。

公开(公告)号：US5562770A

公开(公告)日：1996-10-08

申请号：US343152

申请日：1994-11-22

申请人： Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

发明人： Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

IPC分类号： H01L21/205 ,  C30B25/18 ,  H01L21/8249 ,  H01L27/06

CPC分类号： C30B25/18 ,  Y10S438/938

摘要： The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

摘要翻译： 本发明提供了一种全局应力修饰的方法，其导致半导体衬底上的外延生长的半导体器件层中的位错数目，其中器件层和衬底具有晶格失配。 本发明教导了一种通过从衬底的背面移除薄膜层或者添加薄膜层而向衬底赋予凸曲率的方法，以便在器件层中实现位错密度的降低。

公开(公告)号：US08552500B2

公开(公告)日：2013-10-08

申请号：US13114283

申请日：2011-05-24

申请人： Robert H. Dennard ,  Terence B. Hook

发明人： Robert H. Dennard ,  Terence B. Hook

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84

摘要： A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.

摘要翻译： 具有第一导电类型和顶表面的半导体衬底，设置在顶表面上的氧化物层和设置在氧化物层上的半导体层。 多个晶体管器件设置在半导体层上。 每个晶体管器件包括在源极和漏极之间的沟道，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。 阱区域邻近顶表面形成。 阱区具有第二类导电性。 第一沟槽隔离区域在延伸穿过半导体层的相邻晶体管器件之间。 第二沟槽隔离区域在相反的沟道导电性的相邻晶体管器件之间。