公开(公告)号：US09972678B2

公开(公告)日：2018-05-15

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09852952B2

公开(公告)日：2017-12-26

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170330948A1

公开(公告)日：2017-11-16

申请号：US15668708

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

公开(公告)号：US09741850B1

公开(公告)日：2017-08-22

申请号：US15235320

申请日：2016-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Kuan-Liang Liu ,  Kai-Kuen Chang

IPC: H01L29/745 ,  H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

公开(公告)号：US09224857B2

公开(公告)日：2015-12-29

申请号：US13674146

申请日：2012-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

公开(公告)号：US09034713B2

公开(公告)日：2015-05-19

申请号：US14548248

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L21/266 ,  H01L21/033

CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

公开(公告)号：US20150014768A1

公开(公告)日：2015-01-15

申请号：US13938252

申请日：2013-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Tseng-Hsun Liu ,  Kuan-Yu Chen ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7825

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract translation: 横向双扩散金属氧化物半导体晶体管器件包括其中形成有至少浅沟槽隔离的衬底，包围衬底中的STI的外延层，栅极和漏极区以及形成在衬底中的源极区 在门的相应两侧。 外延层，源极区和漏极区包括第一导电型。 栅极包括形成在基板上的第一部分和延伸到STI中的第二部分。

公开(公告)号：US20140367789A1

公开(公告)日：2014-12-18

申请号：US13918994

申请日：2013-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract translation: 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US20140159155A1

公开(公告)日：2014-06-12

申请号：US14181733

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Chih-Wei Hsu ,  Po-Ching Chuang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract translation: 植入层的布局图案至少包括线性区域和至少非线性区域。 线性区域包括容纳第一掺杂剂的多个第一图案，并且非线性区域包括多个第二图案以容纳第一掺杂剂。 线性区域邻接非线性区域。 此外，线性区域中的第一图案的图案密度小于非线性区域中的第二图案的图案密度。

公开(公告)号：US11195905B2

公开(公告)日：2021-12-07

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： Hsiang-Hua Hsu ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.