公开(公告)号：US10083960B2

公开(公告)日：2018-09-25

申请号：US15637170

申请日：2017-06-29

申请人： Infineon Technologies AG

发明人： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC分类号： H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H03K17/687 ,  H01L29/49 ,  H01L29/78 ,  H01L29/739

CPC分类号： H01L27/0883 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/405 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/7391 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H03K17/687

摘要： A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US10083953B2

公开(公告)日：2018-09-25

申请号：US14591362

申请日：2015-01-07

申请人： FUJI ELECTRIC CO., LTD.

发明人： Masaru Saito

IPC分类号： H01L29/66 ,  H01L27/06 ,  H01L29/735 ,  H01L29/808 ,  H01L29/06 ,  H01L27/098 ,  H01L29/417 ,  H01L29/08

CPC分类号： H01L27/0623 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/41708 ,  H01L29/735 ,  H01L29/808

摘要： Aspects of the invention can include a semiconductor device, control IC for switching power supply and switching power supply unit, which allow input voltage detecting function to be realized without resistor-voltage dividing circuit. An npn-type element consisting of p-type region, collector region and emitter region is included inside of drain region of starting element. On a first interlayer insulating film, aspects of the invention can provide collector electrode wiring of npn-type element, emitter-drain electrode wiring serving as both emitter electrode wiring of npn-type electrode and drain electrode wiring of starting element, source electrode wiring of starting element, and gate electrode wiring of starting element. A first metal wiring can serve both as input terminal of starting element and input terminal of npn-type element is connected to collector electrode wiring. The npn-type element can function as input voltage detecting means for detecting input voltage drop applied to the first wiring.

公开(公告)号：US10079145B2

公开(公告)日：2018-09-18

申请号：US15292328

申请日：2016-10-13

申请人： IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

发明人： Boon Teik Chan ,  Arjun Singh

IPC分类号： H01L21/47 ,  H01L21/027 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC分类号： H01L21/0273 ,  G03F7/0002 ,  H01L21/02356 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/47 ,  H01L29/0692

摘要： The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure. Even further, the method includes performing a self-aligned multiple patterning process.

公开(公告)号：US20180240870A1

公开(公告)日：2018-08-23

申请号：US15955122

申请日：2018-04-17

申请人： Texas Instruments Incorporated

发明人： Marie DENISON ,  Philip L. HOWER ,  Sameer PENDHARKAR

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L21/324 ,  H01L21/761 ,  H01L29/423 ,  H01L21/266

CPC分类号： H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

公开(公告)号：US10038059B2

公开(公告)日：2018-07-31

申请号：US15203981

申请日：2016-07-07

申请人： Renesas Electronics Corporation

发明人： Yoshinori Kaya ,  Yasushi Nakahara

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H03K3/356 ,  H03K17/06

CPC分类号： H01L29/1087 ,  H01L21/76224 ,  H01L27/0922 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7823 ,  H01L29/7835 ,  H01L29/7838 ,  H03K3/356 ,  H03K17/06 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

摘要： An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n−-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n−-type semiconductor region which surrounds the coupling transistor in plan view.

公开(公告)号：US20180211950A1

公开(公告)日：2018-07-26

申请号：US15868592

申请日：2018-01-11

申请人： Leadtrend Technology Corporation

发明人： Kuo-Chin Chiu ,  Chia-Wei Hung

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L27/06 ,  H02H9/04

CPC分类号： H01L27/0262 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/0292 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/735 ,  H01L29/7816 ,  H02H9/046

摘要： An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

公开(公告)号：US20180204841A1

公开(公告)日：2018-07-19

申请号：US15831778

申请日：2017-12-05

申请人： Fuji Electric Co., Ltd.

发明人： Masaharu Yamaji

IPC分类号： H01L27/092 ,  H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/761 ,  H01L21/8234

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/0255 ,  H01L27/0288 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/7817 ,  H01L29/7824

摘要： An HVNMOS having a source follower configuration is disposed in an n− diffusion region that forms an HVJT. The lateral HVNMOS includes a p-type back gate region, source contact region, n+drain region, and gate electrode. The p-type back gate region and source contact region contact a p− isolation region and are separated from p+ common potential regions inside the p− isolation region. The source contact region is electrically connected to the COM electrode pad through a source follower resistor RSF. The p+ common potential regions are electrically connected to the p-type back gate region and source contact region of the HVNMOS through diffusion resistors provided between the p-type back gate region/source contact region of the HVNMOS and the p+ common potential region.

公开(公告)号：US10020392B2

公开(公告)日：2018-07-10

申请号：US15269996

申请日：2016-09-20

申请人： Nuvoton Technology Corporation

发明人： Vivek Ningaraju ,  Po-An Chen ,  Vinay Suresh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861

CPC分类号： H01L29/7819 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/402 ,  H01L29/404 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/7835 ,  H01L29/808 ,  H01L29/8611 ,  H01L29/8618

摘要： Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

公开(公告)号：US10020361B2

公开(公告)日：2018-07-10

申请号：US15201130

申请日：2016-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/205 ,  H01L21/306

CPC分类号： H01L29/0661 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

摘要： A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

公开(公告)号：US20180190763A1

公开(公告)日：2018-07-05

申请号：US15859050

申请日：2017-12-29

申请人： Nuvoton Technology Corporation

发明人： Shao-Ming YANG ,  Ting-Yao CHIEN ,  Chieh-Chih WU ,  Tzu-Chieh LEE ,  Chiu-Chung LAI

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/76224 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate having a first conductive type and a gate region disposed on the substrate. The high-voltage semiconductor also includes a source region and a drain region disposed on two sides of the gate region respectively. The high-voltage semiconductor also includes a linear doped region disposed between the gate region and the drain region, wherein the linear doped region has a nonuniform doping depth and the first conductive type. The high-voltage semiconductor further includes a first buried layer disposed under the source region and having the first conductive type.