公开(公告)号：US20230380150A1

公开(公告)日：2023-11-23

申请号：US18365237

申请日：2023-08-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-SHENG CHANG ,  CHIA-EN HUANG

IPC分类号： H10B20/20 ,  G11C7/18 ,  H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  G11C8/14

CPC分类号： H10B20/20 ,  G11C7/18 ,  H01L23/5252 ,  H01L23/5226 ,  H01L23/5283 ,  G11C8/14

摘要： A method of forming a memory cell includes: providing a semiconductor substrate; forming an active region on the semiconductor substrate; providing a first conductive line over a first portion of the active region to form a first transistor coupled to a bit line of the memory cell; providing a second conductive line over a second portion of the active region to form a second transistor coupled to the bit line of the memory cell; and providing a third conductive line over a third portion of the active region to form a third transistor coupled to a first word line of the memory cell. The first transistor and the second transistor are disposed on two sides of the third transistor, and the third transistor electrically couples the first transistor to the second transistor. A threshold voltage of the second transistor is different from a threshold voltage of the first transistor.

公开(公告)号：US11817386B2

公开(公告)日：2023-11-14

申请号：US17508770

申请日：2021-10-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chih-Wei Huang

IPC分类号： H01L23/525 ,  H10B20/20

CPC分类号： H01L23/5256 ,  H10B20/20

摘要： The present disclosure relates to a method for preparing an electrical fuse (e-fuse) device. The method includes forming a mask layer over a semiconductor substrate, and etching the semiconductor substrate by using the mask layer as a mask to form a fuse link over a semiconductor base. The method also includes epitaxially growing a first bottom anode/cathode region and a second bottom anode/cathode region over the semiconductor base and adjacent to a bottom portion of the fuse link. The fuse link is between the first bottom anode/cathode region and the second anode/cathode region. The method further includes epitaxially growing a top anode/cathode region to replace the mask layer.

公开(公告)号：US20230363151A1

公开(公告)日：2023-11-09

申请号：US18353351

申请日：2023-07-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Shao-Yu Chou ,  Yih Wang

IPC分类号： H10B20/20 ,  H01L23/528 ,  H01L23/532 ,  G11C17/16 ,  G06F30/392 ,  H01L23/525 ,  G11C17/18

CPC分类号： H10B20/20 ,  H01L23/528 ,  H01L23/53271 ,  G11C17/16 ,  G06F30/392 ,  H01L23/5252 ,  G11C17/18

摘要： A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

公开(公告)号：US11810879B2

公开(公告)日：2023-11-07

申请号：US17698794

申请日：2022-03-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Gulbagh Singh ,  Chih-Ming Lee ,  Chi-Yen Lin ,  Wen-Chang Kuo ,  C. C. Liu

IPC分类号： H01L23/00 ,  H01L29/06 ,  H01L23/522 ,  H01L23/58 ,  H01L23/528 ,  H01L21/78 ,  H01L23/532 ,  G06F30/392 ,  G06F30/398 ,  H01L23/544 ,  H01L23/31 ,  H01L21/66 ,  H01L23/525

CPC分类号： H01L24/06 ,  G06F30/392 ,  G06F30/398 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L29/0649 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2223/54426 ,  H01L2224/0239 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03827 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/061 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/2011 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/3512 ,  H01L2924/35121

摘要： A semiconductor structure includes a first contact pad over an interconnect structure. The semiconductor structure further includes a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The semiconductor structure further includes a first buffer layer over the first contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.

公开(公告)号：US20230352333A1

公开(公告)日：2023-11-02

申请号：US17945671

申请日：2022-09-15

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where a top surface of the first level includes a first oxide region and a bottom surface of the second level includes a second oxide region, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, and where the second transistors are raised source drain extension transistors.

公开(公告)号：US11804431B2

公开(公告)日：2023-10-31

申请号：US17670810

申请日：2022-02-14

申请人： X Display Company Technology Limited

发明人： Erich Radauscher ,  Ronald S. Cok ,  Matthew Alexander Meitl ,  Christopher Andrew Bower ,  Christopher Michael Verreen ,  Erik Paul Vick

IPC分类号： H01L23/525 ,  H01L23/544 ,  H01L23/528 ,  H01L27/12

CPC分类号： H01L23/5258 ,  H01L23/528 ,  H01L23/544 ,  H01L27/124

摘要： A parallel redundant system comprises a substrate, a first circuit disposed over the substrate, a first conductor disposed at least partially in a first layer over the substrate and wire routed to the first circuit, a second circuit disposed over the substrate, the second circuit redundant to the first circuit, a second conductor disposed in a second layer over the substrate and electrically connected to the second circuit, the second conductor disposed at least partially over the first conductor, a dielectric layer disposed at least partially between the first layer and the second layer, and a laser weld electrically connecting the first conductor to the second conductor.

公开(公告)号：US11798880B2

公开(公告)日：2023-10-24

申请号：US17486868

申请日：2021-09-27

申请人： Innolux Corporation

发明人： Hirofumi Watsuda ,  Shu-Ming Kuo ,  Chun-Hsien Lin

IPC分类号： H01L23/525 ,  H01L21/768 ,  H01L33/62

CPC分类号： H01L23/525 ,  H01L21/76892 ,  H01L21/76895 ,  H01L33/62

摘要： An electronic device and method of fabricating the same are provided herein. The electronic device includes a first main pad; a second main pad; a first repair line electrically connected to the first main pad; a second repair line electrically connected to the second main pad, wherein the first repair line and the second repair line forms a first weldable region; a first spare pad; a second spare pad; a connection line electrically connected to the second repair line, the first spare pad and the second spare pad; and a first electronic unit disposed on the first main pad and the second main pad.

公开(公告)号：US20230334354A1

公开(公告)日：2023-10-19

申请号：US17722301

申请日：2022-04-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Vivekananda P. Adiga ,  Russell A. Budd ,  Charles Thomas Rettner ,  Stephen M. Gates

IPC分类号： G06N10/00 ,  H01L39/02 ,  H01L23/525

CPC分类号： G06N10/00 ,  H01L39/02 ,  H01L23/5252 ,  H01L23/5256 ,  B82Y10/00

摘要： A superconducting connecting system includes an anti-fuse structure. There is a first superconducting trace having a first segment that is cantilevered over a cavity a substrate. A second superconducting trace having a second segment is cantilevered over the cavity in the substrate. A first auxiliary segment is coupled to the first segment and suspended over the cavity. A second auxiliary segment is coupled to the second segment and suspended over the cavity. The first segment and the second segment face each other and have a predetermined gap therebetween. The first segment and the second segment are configured to receive an output of a laser. An amount of material of the first and second auxiliary segment is based on creating a fuse ball joint that provides an electrical short between the first superconducting trace and the second superconducting trace, upon receiving the output of the laser.

公开(公告)号：US20230326885A1

公开(公告)日：2023-10-12

申请号：US18210392

申请日：2023-06-15

申请人： STMicroelectronics (Rousset) SAS

发明人： Pascal FORNARA

IPC分类号： H01L23/62 ,  H01H85/02 ,  H01L23/525 ,  H01L21/66

CPC分类号： H01L23/62 ,  H01H85/0241 ,  H01L23/5256 ,  H01L22/34 ,  H01H2085/0283

摘要： A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

公开(公告)号：US11784118B2

公开(公告)日：2023-10-10

申请号：US16723901

申请日：2019-12-20

申请人： Intel Corporation

发明人： Eah Loon Alan Chuah ,  Ting Ting Au

IPC分类号： H01L23/50 ,  H01L23/522 ,  H03K19/00 ,  H01L23/62 ,  H01L21/768 ,  H01L21/027 ,  H01L23/525

CPC分类号： H01L23/5226 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/525 ,  H01L23/62 ,  H03K19/0005

摘要： An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a single-ended termination circuit with a first via configuration, a Thevenin termination circuit with a second via configuration, and/or a differential termination circuit with a third configuration.