公开(公告)号：US20150339202A1

公开(公告)日：2015-11-26

申请号：US14717048

申请日：2015-05-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Vlad Fruchter ,  Chi-Ming Yeung

IPC: G06F11/20

CPC classification number: G11C29/765 ,  G06F3/0629 ,  G06F11/0751 ,  G06F11/1008 ,  G11C5/04 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/88 ,  G11C2029/4402

Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

Abstract translation: 响应于具有第一基地址的第一存储器访问事务，从第一DRAM信道检索数据字段和修复字段。 数据字段包括第一数据字段。 修复领域包括存储修复数据的第一修复区域。 修复数据将替换第一个数据字段中的任何数据。 响应于具有第二基地址的第二存储器访问事务，从第二DRAM信道检索修复标签字段。 修复标签字段包括修复标签字段，其指示修复数据被替换存储在第一数据字段中的数据。

公开(公告)号：US20150333740A1

公开(公告)日：2015-11-19

申请号：US14808936

申请日：2015-07-24

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: H03K3/012 ,  G11C7/22 ,  H03L7/24

CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

公开(公告)号：US20150331732A1

公开(公告)日：2015-11-19

申请号：US14707348

申请日：2015-05-08

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Kurt T. Knorpp

IPC: G06F11/07 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0787 ,  G11C11/406 ,  G11C2211/4062

Abstract: An integrated circuit memory device is disclosed. The memory device includes at least one group of storage cells. Logic derives a count of error code correction events for each of the at least one group of storage cells. Storage stores the count. A memory control interface selectively communicates the count to a memory controller.

Abstract translation: 公开了一种集成电路存储器件。 存储器件包括至少一组存储单元。 逻辑导出对于至少一组存储单元中的每一个的错误代码校正事件的计数。 存储存储计数。 存储器控制接口选择性地将计数传送到存储器控制器。

公开(公告)号：US09183920B2

公开(公告)日：2015-11-10

申请号：US14578078

申请日：2014-12-19

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G06F3/00 ,  G11C11/4093 ,  G11C5/04 ,  G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract translation: 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。

公开(公告)号：US09177632B2

公开(公告)日：2015-11-03

申请号：US14714722

申请日：2015-05-18

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G06F12/06

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

公开(公告)号：US20150304136A1

公开(公告)日：2015-10-22

申请号：US14705761

申请日：2015-05-06

Applicant: Rambus Inc.

Inventor： Aliazam Abbasfar

IPC: H04L25/03 ,  H03K5/135

CPC classification number: H04L25/03019 ,  H03K5/135 ,  H03K5/15 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/497

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract translation: 多相部分响应均衡器电路包括采样器电路，其对输入信号进行采样以响应具有不同相位的采样时钟信号产生采样信号。 第一多路复用器电路选择一个采样信号作为第一采样位以表示输入信号。 耦合到第一多路复用器电路的输出的第一存储电路响应于第一时钟信号而存储第一采样位。 第二多路复用器电路根据第一采样位选择一个采样信号作为第二采样位来表示输入信号。 第二存储电路响应于第二时钟信号存储从采样信号中选择的采样位。 存储采样位的第二存储电路与存储第一采样位的第一存储电路之间的时间段基本上大于输入信号中的单位间隔。

公开(公告)号：US09166844B2

公开(公告)日：2015-10-20

申请号：US14073003

申请日：2013-11-06

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract translation: 公开了一种集成电路，其包括从第一信令通道接收双二进制数据符号的接收器电路。 接收机电路包括用于确定符号状态的采样电路和双二进制解码器。 二进制解码器耦合到采样电路，并将检测到的状态转换为PAM2编码符号流。 提供了一个判决反馈均衡器（DFE），其具有与二进制解码器并行地耦合到采样电路的输入。 DFE与采样电路协作以形成反馈路径，使得双二进制解码器在反馈路径的外部。

公开(公告)号：US09160466B2

公开(公告)日：2015-10-13

申请号：US14535006

申请日：2014-11-06

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC: H04B17/00 ,  H04B3/46 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00 ,  H04Q1/20

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract translation: 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

公开(公告)号：US20150281613A1

公开(公告)日：2015-10-01

申请号：US14433003

申请日：2013-09-30

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Michael Guidash ,  Song Xue

IPC: H04N5/378 ,  H04N5/376

CPC classification number: H04N5/378 ,  H04N5/3355 ,  H04N5/35536 ,  H04N5/35545 ,  H04N5/37455 ,  H04N5/3765

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract translation: 在图像传感器系统中实现具有多位采样的图像传感器架构。 响应于入射到感光元件上的光而产生的像素信号被转换成表示像素信号的多位数字值。 如果像素信号超过采样阈值，则光敏元件被复位。 在图像捕获期间，与超过采样阈值的像素信号相关联的数字值被累积到图像数据中。

公开(公告)号：US09135206B2

公开(公告)日：2015-09-15

申请号：US14560357

申请日：2014-12-04

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.

Abstract translation: 集成电路装置向动态随机存取存储器（DRAM）发送指定DRAM内数字控制值的编程的一个或多个命令，数字控制值指示DRAM要耦合到DRAM的数据接口的终端阻抗 DRAM响应于接收到写入命令并且在接收与写入命令相对应的写入数据期间，并且DRAM在接收到与写入命令相对应的写入数据之后与数据接口分离。 此后，集成电路装置向DRAM发送指示在第一时间间隔期间通过DRAM的数据接口对写入数据进行采样的写入命令，并且使得DRAM在第一时间间隔期间将终止阻抗耦合到数据接口 时间间隔，并在第一个时间间隔后将数据接口的终端阻抗解耦。