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    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS
    522.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS 有权

    公开(公告)号：US20250070091A1

    公开(公告)日：2025-02-27

    申请号：US18942886

    申请日：2024-11-11

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

    Abstract: A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

    3D memory devices and structures with memory arrays and metal layers
    523.
    发明授权
    3D memory devices and structures with memory arrays and metal layers 有权

    公开(公告)号：US12225704B2

    公开(公告)日：2025-02-11

    申请号：US18731340

    申请日：2024-06-02

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H10B10/00 ,  G11C16/04 ,  H10B12/00 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.

    3D semiconductor memory devices and structures
    524.
    发明授权
    3D semiconductor memory devices and structures 有权

    公开(公告)号：US12178055B2

    公开(公告)日：2024-12-24

    申请号：US18592383

    申请日：2024-02-29

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one digital to analog converter circuit, and where the device includes a hybrid bonding layer.

    METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE
    525.
    发明申请
    METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE 有权

    公开(公告)号：US20240397720A1

    公开(公告)日：2024-11-28

    申请号：US18793939

    申请日：2024-08-05

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H10B43/27 ,  H10B41/27

    Abstract: A method of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer; providing a second substrate including a second level, the second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer, the third silicon layer has an average thickness of less than 2,000 nm; forming a plurality of second transistors each including a single crystal channel; forming many metal layers interconnecting the plurality of second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second single crystal silicon layer.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS
    527.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS 有权

    公开(公告)号：US20240379553A1

    公开(公告)日：2024-11-14

    申请号：US18783965

    申请日：2024-07-25

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L23/528 ,  H01L21/66 ,  H01L23/522 ,  H10B80/00

    Abstract: A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.

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