公开(公告)号：US20160365456A1

公开(公告)日：2016-12-15

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract translation: 半浮栅晶体管被实现为内置于硅衬底上的垂直FET，其中源极，漏极和沟道彼此垂直对准。 源极和漏极之间的电流流动受到控制栅极和半浮栅的影响。 可以对垂直半浮栅晶体管的源极，漏极和控制栅极端子中的每一个进行正面接触。 垂直半浮栅FET还包括垂直隧道FET和垂直二极管。 垂直半浮栅FET的制造与常规CMOS制造工艺兼容，包括替代金属栅极工艺。 与传统的平面器件相比，低功耗操作允许垂直半浮栅FET提供高电流密度。

公开(公告)号：US20160322479A1

公开(公告)日：2016-11-03

申请号：US14698921

申请日：2015-04-29

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7851

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

Abstract translation: 隧道场效应晶体管由支撑基板上的半导体材料的翅片形成。 半导体材料的鳍片包括源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 栅极电极横跨在通道区域上的翅片上。 在栅电极的每一侧设置侧壁间隔物。 晶体管的源极由从鳍片的源极区域生长并掺杂有第一导电类型的外延锗含量源区域制成。 晶体管的漏极由从鳍片的漏极区域生长并掺杂有第二导电类型的外延硅含量漏极区域制成。

公开(公告)号：US20160293450A1

公开(公告)日：2016-10-06

申请号：US14672664

申请日：2015-03-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Godfrey DIMAYUGA ,  Jefferson Talledo

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

Abstract translation: 半导体器件可以包括具有下导电层，介电层和上导电层的堆叠关系的多层互连板。 电介质层可以具有形成有从底部向上延伸的底部和倾斜侧壁的凹部。 上导电层可以包括跨过倾斜侧壁延伸的上导电迹线，并且下导电层可以包括下导电迹线。 半导体器件可以包括在下导电层和上导电层之间延伸的通孔，由凹槽中的多层互连板承载的IC，将上导电迹线耦合到IC的接合线以及邻近IC的封装材料以及与IC的相邻部分 多层互连板。

公开(公告)号：US09462538B2

公开(公告)日：2016-10-04

申请号：US14520828

申请日：2014-10-22

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： Liwen Chu ,  George A. Vlantis ,  Vincenzo Scarpa

IPC: H04L12/28 ,  H04W48/14 ,  H04W72/12 ,  H04W84/18 ,  H04W40/34 ,  H04W48/08 ,  H04W72/02 ,  H04W84/12 ,  H04W84/22

CPC classification number: H04W48/14 ,  H04W40/34 ,  H04W48/08 ,  H04W72/02 ,  H04W72/1252 ,  H04W84/12 ,  H04W84/18 ,  H04W84/22 ,  Y02D70/142 ,  Y02D70/22

Abstract: The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.

公开(公告)号：US20160284607A1

公开(公告)日：2016-09-29

申请号：US14670800

申请日：2015-03-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

公开(公告)号：US20160284602A1

公开(公告)日：2016-09-29

申请号：US14669055

申请日：2015-03-26

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

Abstract translation: 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

公开(公告)号：US09431934B2

公开(公告)日：2016-08-30

申请号：US14247955

申请日：2014-04-08

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.r.l.

Inventor： Frederic Bonvin ,  Ezio Galbiati

IPC: H02P6/10 ,  G11B19/20 ,  H02P6/08 ,  H02P6/18

CPC classification number: H02P6/10 ,  G11B19/20 ,  H02P6/085 ,  H02P6/18

Abstract: An embodiment of a motor controller includes a motor driver and a signal conditioner. The motor driver is operable to generate a motor-coil drive signal having a first component at a first frequency, and the signal conditioner is coupled to the motor driver and is operable to alter the first component. For example, if the first component of the motor-coil drive signal causes the motor to audibly vibrate (e.g., “whine”), then the signal conditioner may alter the amplitude or phase of the first component to reduce the vibration noise to below a threshold level.

Abstract translation: 马达控制器的实施例包括马达驱动器和信号调节器。 马达驱动器可操作以产生具有第一频率的第一分量的电动机线圈驱动信号，并且信号调节器耦合到马达驱动器并且可操作以改变第一分量。 例如，如果电动机线圈驱动信号的第一分量使得电动机听起来振动（例如，“呜呜”），则信号调节器可以改变第一组件的幅度或相位，以将振动噪声降低到低于 门限等级。

公开(公告)号：US09431540B2

公开(公告)日：2016-08-30

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US09431538B2

公开(公告)日：2016-08-30

申请号：US14950833

申请日：2015-11-24

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMICROELECTRONICS, Inc.

Inventor： Shay Reboh ,  Pierre Morin

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract translation: 制造至少一个晶体管应变通道半导体结构的方法，包括形成牺牲栅极块的步骤和与牺牲栅极块的侧面接触地布置的绝缘间隔物，形成与所述半导体区域的侧面接触的牺牲区域， 所述牺牲区域被配置为在所述半导体区域上施加应变，去除所述绝缘间隔物之间​​的所述牺牲栅极块，用所述绝缘间隔物之间​​的置换栅极块代替所述牺牲栅极块，去除所述牺牲区域， 区域，其与形成晶体管沟道区域的半导体区域相接触，与所述半导体区域的侧面接触。

公开(公告)号：US20160239456A1

公开(公告)日：2016-08-18

申请号：US14625196

申请日：2015-02-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Brian DENG

IPC: G06F13/42 ,  G06F1/10 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  Y02D10/14 ,  Y02D10/151

Abstract: An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.

Abstract translation: 电子设备可以包括系统和串行外设接口（SPI）时钟，以及主机接口，每个主机接口可在主动和非活动状态之间切换，连接到系统时钟的串行控制器和存储器。 从控制器可以基于来自主机的事务请求生成请求活动信号，并使系统时钟，SPI时钟和主机接口中的每一个进入活动状态，将请求数据存储在存储器中，并将主机接口切换到 基于正在存储的请求数据的非活动状态。 串行控制器可以基于请求活动信号处理请求，并且基于正在处理的请求生成请求完成信号。 从控制器可以根据请求完成信号将系统时钟切换到无效状态。 SPI时钟可以根据请求完成信号切换到非活动状态。