公开(公告)号：US09984770B2

公开(公告)日：2018-05-29

申请号：US15140997

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  H03M13/29 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/70 ,  G11C29/72 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  H03M13/2906

Abstract: A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.

公开(公告)号：US20180145040A1

公开(公告)日：2018-05-24

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/573 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L27/088

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US09941010B2

公开(公告)日：2018-04-10

申请号：US15365367

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C8/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C8/12 ,  G11C8/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

公开(公告)号：US20180097058A1

公开(公告)日：2018-04-05

申请号：US15444644

申请日：2017-02-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel ,  Alexandre Sarafianos

IPC: H01L29/06 ,  H03K5/24 ,  H01L29/10 ,  H01L27/06 ,  G06F21/77

CPC classification number: H01L29/0623 ,  G06F21/75 ,  G06F21/77 ,  G06F21/78 ,  G06F21/87 ,  G06F21/88 ,  H01L21/823892 ,  H01L23/57 ,  H01L23/576 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/66181 ,  H03K5/24

Abstract: An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

公开(公告)号：US20180091094A1

公开(公告)日：2018-03-29

申请号：US15436817

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: H03B1/02 ,  H03K3/03 ,  G11C7/06

CPC classification number: H03K3/0315 ,  G05F3/262 ,  G11C7/062 ,  H03K3/011 ,  H03L1/00 ,  H03L5/00 ,  H03L7/0995

Abstract: A device and method can be used to manage the operation of a ring oscillator circuit. A master oscillator circuit generates a master supply voltage. The master supply voltage associated with a stable oscillation rate of the master oscillator circuit. The master oscillator circuit is supplied with current and is structurally identical to the ring oscillator circuit. A capacitive circuit is loaded with a load voltage originating from the master supply voltage. In response to a control signal, the ring oscillator circuit is supplied with a current controlled by a voltage delivered by the capacitive circuit, in such a way as to provide a stable oscillation rate for the ring oscillator circuit.

公开(公告)号：US09899476B2

公开(公告)日：2018-02-20

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06 ,  H01L29/78 ,  H01L27/112

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US09870489B2

公开(公告)日：2018-01-16

申请号：US14970161

申请日：2015-12-15

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Louis Modave ,  Fabrice Marinet ,  Denis Farison

IPC: G06F21/00 ,  G06F21/85 ,  G06F21/73 ,  G06F21/81 ,  G11C27/00

CPC classification number: G06F21/85 ,  G06F21/73 ,  G06F21/81 ,  G11C27/00

Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.

公开(公告)号：US20180003761A1

公开(公告)日：2018-01-04

申请号：US15387370

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/028 ,  G01R31/2882 ,  G04F10/10

Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

公开(公告)号：US20170323684A1

公开(公告)日：2017-11-09

申请号：US15659891

申请日：2017-07-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US20170323683A1

公开(公告)日：2017-11-09

申请号：US15657492

申请日：2017-07-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Victorien Brecte

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C16/08 ,  G11C2207/063

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.