公开(公告)号：US20160141274A1

公开(公告)日：2016-05-19

申请号：US15008444

申请日：2016-01-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5225 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 构造成向所述第一晶体管的一部分提供功率的第一线结构; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及第二线结构，其被构造成向所述第二晶体管的一部分提供电力，其中所述第二线结构与所述第一线结构隔离以向所述第二晶体管的所述部分提供不同的功率电压。

公开(公告)号：US09318408B2

公开(公告)日：2016-04-19

申请号：US14828517

申请日：2015-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H01L23/34 ,  H01L27/06 ,  H01L23/522 ,  H01L23/50

CPC classification number: H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分配结构，其中第二层包括第二时钟分配结构，其中第二时钟分配结构连接到第一层 具有多个贯通层通孔的时钟分配结构，并且其中第二晶体管与具有小于100nm对准误差的第一晶体管对准。

公开(公告)号：US09305867B1

公开(公告)日：2016-04-05

申请号：US14472108

申请日：2014-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/50 ,  H01L23/34 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.

Abstract translation: 一种集成电路装置，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及第二层，包括覆盖所述第二金属层的第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率，以及所述第二晶体管和所述第二金属层之间的连接路径，其中所述连接路径包括 至少一个贯通层通孔，并且其中贯通层通孔具有小于150nm的直径。

公开(公告)号：US09299641B2

公开(公告)日：2016-03-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US20160035722A1

公开(公告)日：2016-02-04

申请号：US14880276

申请日：2015-10-11

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/088 ,  H01L29/45

CPC classification number: H01L29/456 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66704 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

Abstract translation: 一种集成电路器件，包括：包括第一晶体管的第一层; 以及第二层，包括覆盖第一层的第二晶体管，其中第一晶体管面向下并且第二晶体管面向上，并且其中第二层包括直径小于300nm的贯穿层通孔。

公开(公告)号：US09197804B1

公开(公告)日：2015-11-24

申请号：US13274161

申请日：2011-10-14

Applicant: Zvi Or-Bach ,  Paul Lim ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Paul Lim ,  Deepak C. Sekar

IPC: H04N5/225 ,  H04N5/232 ,  H01L27/118 ,  H01L21/70

CPC classification number: H04N5/2253 ,  H01L25/0756 ,  H01L33/382 ,  H01L2924/0002 ,  H04N5/2254 ,  H04N5/2258 ,  H04N5/23212 ,  H04N5/35563 ,  H04N9/045 ,  H01L2924/00

Abstract: A camera system including, a first image sensor array and a second image sensor array wherein the first image sensor array is designed for a first focal plane in front of the camera, and the second image sensor array is designed for a second focal plane in front of the camera, wherein the distance to the first focal plane is substantially different than the distance to the second focal plane.

Abstract translation: 一种照相机系统，包括第一图像传感器阵列和第二图像传感器阵列，其中所述第一图像传感器阵列被设计用于在所述相机前面的第一焦平面，并且所述第二图像传感器阵列被设计为在前面的第二焦平面 其中到第一焦平面的距离与到第二焦平面的距离基本上不同。

公开(公告)号：US09136153B2

公开(公告)日：2015-09-15

申请号：US13492395

申请日：2012-06-08

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并且包括铝或铜的第一互连层; 包括第二晶体管的第二层; 其中所述第二晶体管与所述第一晶体管对准，具有小于40nm的对准误差，并且其中所述第二层覆盖所述第一互连层，并且其中所述第二晶体管中的至少一个具有背偏置结构， 至少一个第二晶体管的性能。

公开(公告)号：US08994404B1

公开(公告)日：2015-03-31

申请号：US13796930

申请日：2013-03-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H03K19/096

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection; the first layer includes a first clock distribution structure, the first clock distribution structure includes a first clock origin, the second layer includes a second clock distribution structure, the second clock distribution structure includes a second clock origin, and the second clock origin is feeding the first clock origin.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 第二层，包括第二晶体管，第二晶体管覆盖第一层互连层; 所述第一层包括第一时钟分配结构，所述第一时钟分配结构包括第一时钟源，所述第二层包括第二时钟分配结构，所述第二时钟分配结构包括第二时钟源，并且所述第二时钟源正在馈送 第一时钟源。

公开(公告)号：US20150054090A1

公开(公告)日：2015-02-26

申请号：US14506160

申请日：2014-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Abstract translation: 一种基于3D IC的系统，包括：包括第一晶体管的第一层; 覆盖第一层的第二层，第二层包括多个第二晶体管，其中第二层包括直径小于400nm的至少一个至第二层，并且其中多个第二晶体管中的至少一个 形成包括背偏置区域的两个稳定状态存储单元。

公开(公告)号：US08956959B2

公开(公告)日：2015-02-17

申请号：US13246157

申请日：2011-09-27

Applicant: Deepak C. Sekar ,  Zvi Or-Bach

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L21/20 ,  H01L21/84 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L27/22 ,  H01L27/24 ,  H01L29/78 ,  H01L27/105 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括由第一光刻步骤限定的半导体区域的第一单晶层; 然后用隔离层覆盖第一单晶层; 在形成第一单晶层之后制备第二单晶层; 转移覆盖隔离层的第二单晶层; 然后执行第二光刻步骤，图案化第一单晶层的部分，作为在第一单晶层中形成至少一个晶体管的一部分。