公开(公告)号：US20190251855A1

公开(公告)日：2019-08-15

申请号：US15896808

申请日：2018-02-14

申请人： Ravi Kokku ,  Tamer E. Abuelsaad ,  Prasenjit Dey ,  Satyanarayana V. Nitta ,  Miles Ludwig ,  Emily Reardon ,  James H. Gray

发明人： Ravi Kokku ,  Tamer E. Abuelsaad ,  Prasenjit Dey ,  Satyanarayana V. Nitta ,  Miles Ludwig ,  Emily Reardon ,  James H. Gray

IPC分类号： G09B7/04 ,  G09B5/12 ,  G09B19/04 ,  G06N5/02

CPC分类号： G09B7/04 ,  G06N5/022 ,  G09B5/12 ,  G09B19/04

摘要： A combination of knowledge representation and retrieval, assessments and personalization for a tutoring platform that provides an automated phased word exposition method for vocabulary learning and enable learners to learn words (or any learning objective) with sufficient proficiency and without excessive repetition. The phased learning objective method implements a moving average model that models the learner across multiple dimensions (e.g. reading, listening, writing, speaking) such that the platform is confident of the learner's understanding, while using minimal assessment doses, and such that the understanding transfers across experiences. The method implemented provides for multiple learning and assessment activities for a learning objective and leverages the same learner model for each learning dimension. Each word of a word set passes through learning and assessment-only phases for statistically significant evidence of learning. The model derived from the phased word expansion can be shared across applications, toys and tangibles that learners interact with.

公开(公告)号：US09059251B2

公开(公告)日：2015-06-16

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08779600B2

公开(公告)日：2014-07-15

申请号：US13344009

申请日：2012-01-05

申请人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Satyanarayana V. Nitta

发明人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Satyanarayana V. Nitta

IPC分类号： H01L29/40

CPC分类号： H01L23/5384 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249969 ,  H01L2924/00

摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

摘要翻译： 一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。 电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。 该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。 电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分 。

公开(公告)号：US08383507B2

公开(公告)日：2013-02-26

申请号：US13351370

申请日：2012-01-17

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US20120068344A1

公开(公告)日：2012-03-22

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US07968450B2

公开(公告)日：2011-06-28

申请号：US12543999

申请日：2009-08-19

申请人： Azeez J. Bhavnagarwala ,  Stephen V. Kosonocky ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

发明人： Azeez J. Bhavnagarwala ,  Stephen V. Kosonocky ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/768

CPC分类号： H01L21/76801 ,  G11C11/412 ,  H01L23/53295 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

摘要翻译： 制造在一组区域中具有比在同一微电子芯片上的其它区域更高的互连电容的混合互连结构的方法。 提供了几种制造这种结构的方法。 描述了这样的混合互连结构的电路实现，其能够增加静态噪声容限并且减少SRAM单元中的泄漏以及用于这种芯片中的SRAM和逻辑的公共电源电压。 还教导了能够将这些电路优点与更高的互连性能速度和优异的机械鲁棒性相结合的方法。

公开(公告)号：US20100200960A1

公开(公告)日：2010-08-12

申请号：US12689479

申请日：2010-01-19

申请人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

发明人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

IPC分类号： H01L23/544 ,  H01L21/302

CPC分类号： H01L23/585 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

摘要翻译： 形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于 在互连堆叠层中的格子工作裂纹结构下。 深沟槽可以保持未填充，或者可以用介电材料或导体填充。 深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

公开(公告)号：US20100187689A1

公开(公告)日：2010-07-29

申请号：US12695515

申请日：2010-01-28

申请人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3178 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05552

摘要： An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

摘要翻译： 在无源区域中包括有源区域的无源区域和切割线的集成电路包括钝化层，其在氧化物层上包括外部氮化物层。 该集成电路还包括钝化层下方和被动区域中的裂纹停止点以及有源区域中的焊球。 钝化层在其中形成的沟槽位于比切割线更远离有源区域并且比切割线更靠近有源区的位置，沟槽完全穿过外部氮化物层，并且至少部分地 通过氧化层。

公开(公告)号：US07749892B2

公开(公告)日：2010-07-06

申请号：US11564358

申请日：2006-11-29

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Son V. Nguyen ,  Alfred Grill ,  Satyanarayana V. Nitta ,  Darryl D. Restaino ,  Terry A. Spooner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

摘要翻译： 提供的互连，其包括具有顶表面和下表面的铜导体，其中帽形成在金属导体的顶表面上。 盖由双层叠或多层薄膜形成，层压膜包括超紫（UV）阻挡膜和扩散阻挡膜。 扩散阻挡膜和UV阻挡膜可以通过中间膜分离。