公开(公告)号：US20190251855A1

公开(公告)日：2019-08-15

申请号：US15896808

申请日：2018-02-14

申请人： Ravi Kokku ,  Tamer E. Abuelsaad ,  Prasenjit Dey ,  Satyanarayana V. Nitta ,  Miles Ludwig ,  Emily Reardon ,  James H. Gray

发明人： Ravi Kokku ,  Tamer E. Abuelsaad ,  Prasenjit Dey ,  Satyanarayana V. Nitta ,  Miles Ludwig ,  Emily Reardon ,  James H. Gray

IPC分类号： G09B7/04 ,  G09B5/12 ,  G09B19/04 ,  G06N5/02

CPC分类号： G09B7/04 ,  G06N5/022 ,  G09B5/12 ,  G09B19/04

摘要： A combination of knowledge representation and retrieval, assessments and personalization for a tutoring platform that provides an automated phased word exposition method for vocabulary learning and enable learners to learn words (or any learning objective) with sufficient proficiency and without excessive repetition. The phased learning objective method implements a moving average model that models the learner across multiple dimensions (e.g. reading, listening, writing, speaking) such that the platform is confident of the learner's understanding, while using minimal assessment doses, and such that the understanding transfers across experiences. The method implemented provides for multiple learning and assessment activities for a learning objective and leverages the same learner model for each learning dimension. Each word of a word set passes through learning and assessment-only phases for statistically significant evidence of learning. The model derived from the phased word expansion can be shared across applications, toys and tangibles that learners interact with.

公开(公告)号：US08896120B2

公开(公告)日：2014-11-25

申请号：US12768267

申请日：2010-04-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/02 ,  H01L21/31 ,  H01L21/027 ,  H01L23/522

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/0276 ,  H01L21/31 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地，本文所述的方法提供了内置于可光图案化的低k材料中的互连结构，其中不同深度的气隙通过光刻图案中的低k材料中的光刻来定义。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08624323B2

公开(公告)日：2014-01-07

申请号：US13149797

申请日：2011-05-31

申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

公开(公告)号：US08431486B2

公开(公告)日：2013-04-30

申请号：US12853537

申请日：2010-08-10

申请人： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin Fletcher ,  Eric A. Joseph ,  Satyanarayana V. Nitta

发明人： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin Fletcher ,  Eric A. Joseph ,  Satyanarayana V. Nitta

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

摘要翻译： 本公开提供了形成到电气设备的互连的方法。 在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点 所述至少一个电气设备。 在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。 蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。 梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。

公开(公告)号：US20130009282A1

公开(公告)日：2013-01-10

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/06

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US20120329287A1

公开(公告)日：2012-12-27

申请号：US13603008

申请日：2012-09-04

申请人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

发明人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

IPC分类号： H01L21/312

CPC分类号： H01L23/5329 ,  C23C16/401 ,  C23C16/505 ,  C23C16/511 ,  C23C16/56 ,  H01J2237/336 ,  H01J2237/338 ,  H01J2237/3382 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CHx)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.

摘要翻译： 通过在不饱和烃环境中后处理，使四面体应变增加引起的应力变化最小化的多孔SiCOH介电膜。 p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键合部分。 此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。 由于气孔包括其中x为1,2或3的稳定的交联 - （CH x） - 链，因此制备柔性的p-SiCOH介电膜。 介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。

公开(公告)号：US20120261828A1

公开(公告)日：2012-10-18

申请号：US13088054

申请日：2011-04-15

申请人： ROBERT L. BRUCE ,  Qinghuang Lin ,  Alshakim Nelson ,  Satyanarayana V. Nitta ,  Dirk Pfeiffer ,  Jitendra S. Rathore

发明人： ROBERT L. BRUCE ,  Qinghuang Lin ,  Alshakim Nelson ,  Satyanarayana V. Nitta ,  Dirk Pfeiffer ,  Jitendra S. Rathore

IPC分类号： H01L21/283 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a patterned and cured dielectric layer located directly on a surface of a patterned permanent antireflective coating. The patterned and cured dielectric layer and the permanent antireflective coating form shaped openings. The shaped openings include an inverse profile which narrows towards a top of the shaped openings. A conductive structure fills the shaped openings wherein the patterned and cured dielectric layer and the permanent antireflective coating each have a conductively filled region.

摘要翻译： 互连结构包括直接位于图案化的永久抗反射涂层的表面上的图案化和固化的电介质层。 图案化和固化的介电层和永久性抗反射涂层形成成形的开口。 成形的开口包括朝向成形开口的顶部变窄的反向轮廓。 导电结构填充成形开口，其中图案化和固化的介电层和永久性抗反射涂层各自具有导电填充区域。

公开(公告)号：US08288268B2

公开(公告)日：2012-10-16

申请号：US12770254

申请日：2010-04-29

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/40 ,  H01L21/4763

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。

公开(公告)号：US20110260326A1

公开(公告)日：2011-10-27

申请号：US12768267

申请日：2010-04-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/0276 ,  H01L21/31 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地，本文所述的方法提供了内置于可光图案化的低k材料中的互连结构，其中不同深度的气隙通过光刻图案中的低k材料中的光刻来定义。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。