公开(公告)号：US11862173B2

公开(公告)日：2024-01-02

申请号：US17332725

申请日：2021-05-27

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/28 ,  G10L15/22 ,  G10L25/48 ,  G06F3/16 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/32 ,  G10L15/08

CPC classification number: G10L15/28 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  G10L15/22 ,  G10L25/48 ,  G10L2015/088 ,  Y02D10/00

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US10929222B2

公开(公告)日：2021-02-23

申请号：US16405362

申请日：2019-05-07

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Sukalpa Biswas ,  Jeffrey R. Wilcox ,  Farid Nemati

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G06F12/1072 ,  G06F12/121 ,  G06F12/12 ,  G06F12/06 ,  G06F12/126 ,  G11C29/04 ,  G11C29/44

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

公开(公告)号：US10795818B1

公开(公告)日：2020-10-06

申请号：US16418811

申请日：2019-05-21

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Per H. Hammarlund ,  Brian P. Lilly ,  Michael Bekerman ,  James Vash ,  Manu Gulati ,  Benjamin K. Dodge

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817

Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

公开(公告)号：US10431224B1

公开(公告)日：2019-10-01

申请号：US16397057

申请日：2019-04-29

Applicant: Apple Inc. ,  Diane Culbert

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G10L15/28 ,  G06F1/3287 ,  G06F1/3228 ,  G06F3/16 ,  G06F1/32 ,  G10L15/08 ,  G10L25/48

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US10042701B2

公开(公告)日：2018-08-07

申请号：US15273208

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Sukalpa Biswas ,  Jeffrey R. Wilcox ,  Farid Nemati

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G06F12/1072 ,  G06F12/121 ,  G06F12/12 ,  G06F12/06 ,  G06F12/126 ,  G11C29/04 ,  G11C29/44

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

公开(公告)号：US09928838B2

公开(公告)日：2018-03-27

申请号：US15482142

申请日：2017-04-07

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck ,  Alexei E. Kosut ,  Girault W. Jones ,  Timothy J. Millet

IPC: G10L15/28 ,  G10L19/00 ,  G10L15/22 ,  G10L15/08

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

公开(公告)号：US20180032281A1

公开(公告)日：2018-02-01

申请号：US15225343

申请日：2016-08-01

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

公开(公告)号：US09811142B2

公开(公告)日：2017-11-07

申请号：US14499807

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Erik P. Machnicki ,  Keith Cox ,  Timothy J. Millet

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

公开(公告)号：US09698797B1

公开(公告)日：2017-07-04

申请号：US15210852

申请日：2016-07-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Suhas Kumar Suvarna Ramesh ,  Venkata Ramana Malladi ,  Thomas H. Huang ,  Rakesh L. Notani ,  Robert E. Jeter ,  Kai Lun Hsiung

IPC: H03L7/00 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/23

Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

公开(公告)号：US20170177256A1

公开(公告)日：2017-06-22

申请号：US15447328

申请日：2017-03-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F3/06 ,  G06F9/44 ,  G06F13/16 ,  G06F13/42 ,  G11C11/406 ,  G06F13/40

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.