公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US06776850B2

公开(公告)日：2004-08-17

申请号：US10165541

申请日：2002-06-08

申请人： Miao-Cheng Liao ,  Ying-Lang Wang ,  Hung-Hsin Liang ,  Hsiang-Sheng Cheng ,  Sheng-Te Shu ,  Chih-Yuan Yang

发明人： Miao-Cheng Liao ,  Ying-Lang Wang ,  Hung-Hsin Liang ,  Hsiang-Sheng Cheng ,  Sheng-Te Shu ,  Chih-Yuan Yang

IPC分类号： C23C1600

CPC分类号： H01L21/67126 ,  C23C16/4401 ,  C23C16/4407

摘要： A preventive maintenance tool which may be installed on a metal chemical vapor deposition (CVD) chamber to prevent escape of contaminating and toxic gases from the chamber interior during preventative maintenance (PM) cleaning of the chamber. The tool comprises a cylindrical tool body which fits to the lid O-ring of the chamber to form a gas-tight seal therewith; a vacuum line connector nipple extending from the body for connection to a vacuum line; and a lid panel rotatably mounted in the body and fitted with a pair of hinged closing panels for reversibly sealing the chamber and facilitating chamber cleaning.

摘要翻译： 预防性维护工具，其可以安装在金属化学气相沉积（CVD）室上，以防止腔室内的污染和有毒气体从室内预防性维护（PM）清洗过程中逸出。 该工具包括圆柱形工具主体，该圆柱形工具主体适合于室的盖O形环以与其形成气密密封; 从主体延伸以连接到真空管线的真空管线连接器接头; 以及盖板，其可旋转地安装在主体中并且装配有一对铰接的关闭板，用于可逆地密封室并促进室清洁。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US06436791B1

公开(公告)日：2002-08-20

申请号：US09880259

申请日：2001-06-14

申请人： Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

发明人： Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76224

摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.

摘要翻译： 一种形成浅沟槽隔离结构的方法，包括以下步骤。 提供具有上表面的基板。 衬底氧化层形成在衬底上。 在衬垫氧化物层上形成氮化物层。 氮化物层具有上表面。 通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。 沟槽具有底部和侧壁。 在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。 从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。 去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。 外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。 在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间​​的界面。 蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

公开(公告)号：US06395635B1

公开(公告)日：2002-05-28

申请号：US09206741

申请日：1998-12-07

申请人： Ying-Lang Wang ,  Jowei Dun

发明人： Ying-Lang Wang ,  Jowei Dun

IPC分类号： H01L21302

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.

摘要翻译： 提供了一种CMP工艺，用于减少钨镶嵌残余物并消除正在抛光的表面内的表面划痕。 ILD的三步抛光程序之后是ILD的两步抛光程序。 三步抛光程序通过从抛光表面去除镶嵌残留物来减少设备缺陷计数。 两步抛光程序减少抛光表面内的微刮痕，从而提高设备的生产能力。 对IMD应用两步抛光程序。 应用氧化物抛光，并由三步抛光程序组成，其后是两步抛光程序。

公开(公告)号：US06232043B1

公开(公告)日：2001-05-15

申请号：US09318471

申请日：1999-05-25

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

摘要翻译： 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。

公开(公告)号：US08772899B2

公开(公告)日：2014-07-08

申请号：US13409924

申请日：2012-03-01

申请人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Shiu-Ko JangJian ,  Min Hao Hong ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： H01L31/00 ,  H01L31/02

CPC分类号： H01L27/1464 ,  H01L27/14687

摘要： Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter.

摘要翻译： 公开了用于背面照明（BSI）图像传感器装置的方法和装置。 在包括感光二极管的基板上形成BSI传感器装置。 衬底可以在背面变薄，则可以在衬底的背面上形成B掺杂的Epi-Si（Ge）层。 另外的层可以形成在B掺杂的Epi-Si（Ge）层上，例如金属屏蔽层，电介质层，微透镜和滤色器。

公开(公告)号：US08470390B2

公开(公告)日：2013-06-25

申请号：US11972785

申请日：2008-01-11

申请人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B05D5/12 ,  C23C14/00

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.

摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

公开(公告)号：US08455883B2

公开(公告)日：2013-06-04

申请号：US13111732

申请日：2011-05-19

申请人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

发明人： Miao-Cheng Liao ,  Min Hao Hong ,  Hsiang Hsiang Ko ,  Kei-Wei Chen ,  Ying-Lang Wang

IPC分类号： H01L29/15 ,  H01L31/052 ,  H01L21/331

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

摘要翻译： 公开了一种制造半导体器件的半导体器件和方法。 用于制造半导体器件的示例性半导体器件和方法增强载流子迁移率。 该方法包括提供衬底并在衬底上形成电介质层。 该方法还包括在电介质层内形成第一沟槽，其中第一沟槽延伸穿过电介质层并且外延（epi）在第一沟槽内生长第一有源层，并用辐射能选择性地固化与第一沟槽相邻的介电层 活动层

公开(公告)号：US08435893B1

公开(公告)日：2013-05-07

申请号：US13304235

申请日：2011-11-23

申请人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/44

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

摘要翻译： 提供一种用于形成半导体器件的系统和方法。 一个实施例包括在硅化物区域和衬底之间的过渡区域上形成衬底上的硅化物区域。 控制硅化物前体材料层的厚度以及退火条件，使得在过渡区域内的一种原子种类的比例比另一种原子种类更大，从而增加过渡区域内的空穴迁移率。