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    Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors
    52.
    发明授权
    Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors 有权
    形成用于应变CMOS垂直纳米线场效应晶体管的对称应力衬垫

    公开(公告)号：US09570552B1

    公开(公告)日：2017-02-14

    申请号：US15076842

    申请日：2016-03-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Tek Po Rinus Lee ,  Jinping Liu

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

    CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7843 ,  H01L29/785

    Abstract: A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer.

    Abstract translation: 提供形成对称应力衬垫以维持CMOS垂直NW FET中的应变以及所得到的器件的方法。 实施例包括在衬底的上表面上提供掺杂半导体层; 在所述掺杂半导体层上提供半导体纳米线; 在围绕半导体纳米线的掺杂半导体层上形成第一应力层; 在所述半导体纳米线的相对侧上的所述第一应力层的一部分上形成栅极电极层; 在栅极电极层和半导体纳米线之间的第一应力层上形成栅极电介质层; 在所述第一应力层的剩余部分上形成氧化物层; 在氧化物层，栅极电介质层和栅极电极层上形成第二应力层; 以及与栅电极层，半导体纳米线和掺杂半导体层形成接触。

    INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME
    54.
    发明申请
    INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME 有权
    具有改进的掺杂通道区域的FINFET的集成电路及其制造方法

    公开(公告)号：US20150294915A1

    公开(公告)日：2015-10-15

    申请号：US14749245

    申请日：2015-06-24

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

    IPC: H01L21/8238

    CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

    Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

    Methods of forming gate structures for transistor devices for CMOS applications
    55.
    发明授权
    Methods of forming gate structures for transistor devices for CMOS applications 有权
    为CMOS应用形成晶体管器件的栅极结构的方法

    公开(公告)号：US09105497B2

    公开(公告)日：2015-08-11

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET
    56.
    发明申请
    METHOD TO FORM WRAP-AROUND CONTACT FOR FINFET 有权
    形成FINFET封边接点的方法

    公开(公告)号：US20150200260A1

    公开(公告)日：2015-07-16

    申请号：US14156745

    申请日：2014-01-16

    Applicant: GlobalFoundries Inc.

    Inventor： Hong Yu ,  Jinping Liu

    IPC: H01L29/40 ,  H01L29/417 ,  H01L21/768

    CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

    Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

    Abstract translation: 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。

    Concurrently forming nFET and pFET gate dielectric layers
    57.
    发明授权
    Concurrently forming nFET and pFET gate dielectric layers 有权
    同时形成nFET和pFET栅极电介质层

    公开(公告)号：US09059315B2

    公开(公告)日：2015-06-16

    申请号：US13732455

    申请日：2013-01-02

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    TRANSISTOR COMPRISING AN AIR GAP POSITIONED ADJACENT A GATE ELECTRODE
    59.
    发明申请
    TRANSISTOR COMPRISING AN AIR GAP POSITIONED ADJACENT A GATE ELECTRODE 审中-公开

    公开(公告)号：US20200066899A1

    公开(公告)日：2020-02-27

    申请号：US16664056

    申请日：2019-10-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

    Method for forming replacement air gap
    60.
    发明授权
    Method for forming replacement air gap 有权

    公开(公告)号：US10535771B1

    公开(公告)日：2020-01-14

    申请号：US16016828

    申请日：2018-06-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

    Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

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