公开(公告)号：US20160049402A1

公开(公告)日：2016-02-18

申请号：US14461769

申请日：2014-08-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing LIU ,  Chun-chen YEH ,  Ruilong XIE ,  Xiuyu CAl

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/167

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.

Abstract translation: 制造半导体器件的方法可以包括形成彼此横向相邻的第一和第二半导体区域，并且每个半导体区域包括第一半导体材料。 该方法还可以包括在包括第一半导体材料和第一掺杂剂的第二半导体区域上方形成原位掺杂的穿通阻挡层，并且在穿通阻挡层上方形成半导体缓冲层， 通过阻挡层包括第一半导体材料。 该方法还可以包括在半导体缓冲层之上形成第三半导体区域，其中第三半导体区域包括与第一半导体材料不同的第二半导体材料。 此外，可以从第一半导体区域形成至少一个第一鳍片，并且可以从第二半导体区域，穿通阻挡层，半导体缓冲层和第三半导体区域形成至少一个第二鳍片。

公开(公告)号：US20140110794A1

公开(公告)日：2014-04-24

申请号：US13654717

申请日：2012-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Pranatharthiharan BALASUBRAMANIAN ,  Shom PONOTH

IPC: H01L21/283 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20200176444A1

公开(公告)日：2020-06-04

申请号：US16204506

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei XU ,  Hui ZANG ,  Ruilong XIE ,  Haiting WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

公开(公告)号：US20190362978A1

公开(公告)日：2019-11-28

申请号：US15987018

申请日：2018-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heimanu Niebojewski ,  Ruilong XIE ,  Andrew M. Greene

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.

公开(公告)号：US20190214298A1

公开(公告)日：2019-07-11

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20190206682A1

公开(公告)日：2019-07-04

申请号：US15860161

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Yi QI

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0335 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0332

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cut margin structures and methods of manufacture. The method includes: forming a plurality of patterned hardmask stacks containing at least a semiconductor layer and a capping layer; removing a portion of a first patterned hardmask stack and a margin of an adjacent hardmask stack of the plurality of the patterned hardmask stacks; and selectively growing material on the margin of the adjacent hardmask stack.

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.

公开(公告)号：US20180374935A1

公开(公告)日：2018-12-27

申请号：US16056934

申请日：2018-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20180233412A1

公开(公告)日：2018-08-16

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Nigel CAVE

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/28518 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US20180122644A1

公开(公告)日：2018-05-03

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Hoon KIM

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.