公开(公告)号：US09412822B2

公开(公告)日：2016-08-09

申请号：US14200737

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

公开(公告)号：US20160225659A1

公开(公告)日：2016-08-04

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片，所述翅片具有包含氧化阻滞注入区域的下部第一部分和基本上不含氧化延迟注入区域的上部第二部分 在翅片的上部的相对侧上形成侧壁间隔物，形成邻近侧壁间隔物和鳍片下部的上部第二部分的第一绝缘材料层，并且第一绝缘材料层 位置，进行热退火处理以将与第一绝缘材料层接触的翅片的上部第二部分的部分转换成位于翅片的下部第一部分下方的翅片下方的氧化物翅片隔离区域。

公开(公告)号：US09406545B2

公开(公告)日：2016-08-02

申请号：US14735466

申请日：2015-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/7621 ,  H01L21/76205 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A silicon-carbon alloy layer and a silicon-germanium alloy layer are sequentially formed on a silicon-containing substrate with epitaxial alignment. Trenches are formed in the silicon-germanium alloy layer by an anisotropic etch employing a patterned hard mask layer as an etch mask and the silicon-carbon alloy layer as an etch stop layer. Fin-containing semiconductor material portions are formed on a bottom surface and sidewalls of each trench with epitaxial alignment with the silicon-germanium alloy layer and the silicon-carbon alloy layer. The hard mask layer and the silicon-germanium alloy layer are removed, and an oxygen-impermeable spacer is formed on sidewalls of each fin-containing semiconductor material portion. Physically exposed semiconductor portions are converted into semiconductor oxide portions, and the oxygen-impermeable spacers are removed. The remaining portions of the fin-containing semiconductor portions include semiconductor fins, which can be employed to form semiconductor devices.

公开(公告)号：US20160218043A1

公开(公告)日：2016-07-28

申请号：US15092233

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L21/266 ,  H01L29/32 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

公开(公告)号：US09391091B2

公开(公告)日：2016-07-12

申请号：US14696693

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L21/425 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

Abstract: An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

公开(公告)号：US20160190140A1

公开(公告)日：2016-06-30

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L27/108 ,  H01L21/84 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract translation: 公开了用于深沟槽电容器连接的结构和方法。 该结构包括电容器导体的直径减小的顶部。 这增加了相邻深沟槽电容器之间的有效间隔。 然后沉积硅化物或附加的多晶硅以完成深沟槽电容器和相邻晶体管之间的连接。

公开(公告)号：US09373507B2

公开(公告)日：2016-06-21

申请号：US14618498

申请日：2015-02-10

Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/225 ,  H01L21/761 ,  H01L29/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US09356046B2

公开(公告)日：2016-05-31

申请号：US14088025

申请日：2013-11-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Ali Khakifirooz

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924

Abstract: Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.

Abstract translation: 本发明的实施例提供了一种用于形成CMOS场效应晶体管的改进的结构和方法。 在实施例中，在半导体结构的PFET侧形成硅锗（SiGe），而在半导体结构的NFET侧设置硅。 在PFET和NFET之间形成窄的隔离区。 NFET鳍由硅构成，PFET鳍由硅锗构成。

公开(公告)号：US09324795B2

公开(公告)日：2016-04-26

申请号：US14751493

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09299777B2

公开(公告)日：2016-03-29

申请号：US14751706

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.