公开(公告)号：US20190378763A1

公开(公告)日：2019-12-12

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Ruilong XIE ,  Shesh Mani PANDEY ,  Hui ZANG ,  Garo Jacques DERDERIAN ,  Scott BEASOR

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20190355838A1

公开(公告)日：2019-11-21

申请号：US15980436

申请日：2018-05-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Ruilong XIE ,  Scott BEASOR

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28

Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an α-Si layer in a recess over the epi S/D; forming an oxide layer over the α-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and α-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.

公开(公告)号：US20180233580A1

公开(公告)日：2018-08-16

申请号：US15432710

申请日：2017-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  John H. ZHANG ,  Stan TSAI

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor gate structures with gate height scaling and methods of manufacture. The method includes: forming at least one dummy gate structure with hardmask material; forming a plurality of materials over source and drain regions on sides of the at least one dummy gate structure; removing upper materials of the hardmask material such that a first material of the hardmask material remains on the dummy gate structure and in combination with a blocking material of the plurality of materials maintains a uniform gate height; forming a replacement gate structure by removing remaining material of the dummy gate structure to form a trench and depositing replacement gate material in the trench; and forming contacts to the source and drain regions.

公开(公告)号：US20180090598A1

公开(公告)日：2018-03-29

申请号：US15280451

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Tenko YAMASHITA ,  Kangguo CHENG ,  Chun-Chen YEH

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L21/033 ,  H01L27/088

CPC classification number: H01L29/66666 ,  H01L21/0332 ,  H01L21/0337 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66545 ,  H01L29/7827

Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height. The method further includes forming a top source/drain layer over the vertical channel, replacing the dummy gate with a metal gate, and forming self-aligned source, drain and gate contacts.

公开(公告)号：US20180019313A1

公开(公告)日：2018-01-18

申请号：US15718958

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/285 ,  H01L21/8238 ,  H01L21/266 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.

公开(公告)号：US20160254158A1

公开(公告)日：2016-09-01

申请号：US14634483

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-Gyu SUNG ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

Abstract translation: 共同制造具有不同阈值电压的非平面（即，三维）半导体器件包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，至少两个栅极结构， 每个栅极结构包括一个衬有介电材料并部分填充有功函材料的栅极开口，一部分功函材料被凹入。 共同制造还包括在一个或多个且少于所有的栅极开口中产生至少一个共形阻挡层，用导电材料填充栅极开口，以及修改至少一个且小于所有填充的栅极开口的功函数 门结构。

公开(公告)号：US20140110794A1

公开(公告)日：2014-04-24

申请号：US13654717

申请日：2012-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Pranatharthiharan BALASUBRAMANIAN ,  Shom PONOTH

IPC: H01L21/283 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20200176444A1

公开(公告)日：2020-06-04

申请号：US16204506

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei XU ,  Hui ZANG ,  Ruilong XIE ,  Haiting WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

公开(公告)号：US20190362978A1

公开(公告)日：2019-11-28

申请号：US15987018

申请日：2018-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heimanu Niebojewski ,  Ruilong XIE ,  Andrew M. Greene

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.

公开(公告)号：US20190214298A1

公开(公告)日：2019-07-11

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. STEPHENS ,  Daniel CHANEMOUGAME ,  Ruilong XIE ,  Lars W. LIEBMANN ,  Gregory A. NORTHROP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.