METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION
    51.
    发明申请
    METHODS FOR MODELING OF FINFET WIDTH QUANTIZATION 有权
    FINFET宽度量化建模方法

    公开(公告)号:US20140201699A1

    公开(公告)日:2014-07-17

    申请号:US13741490

    申请日:2013-01-15

    CPC classification number: G06F17/50 G06F17/5009 G06F17/5036

    Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

    Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件(IOFF),并且确定用于关断finFET器件(VOFF)的电压模型 )。 该方法还包括将FinFET模型拟合到VOFF。

    SELF-ALIGNED CONTACTS
    54.
    发明申请
    SELF-ALIGNED CONTACTS 有权
    自对准联系人

    公开(公告)号:US20130230978A1

    公开(公告)日:2013-09-05

    申请号:US13859284

    申请日:2013-04-09

    Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

    Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法,并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上,封装牺牲层,第二层和聚 -Si,通过形成在次级层中的开口去除牺牲层,并在至少由牺牲层正式占据的空间内形成硅化物。

    Multi-Gate Field Effect Transistor with A Tapered Gate Profile
    55.
    发明申请
    Multi-Gate Field Effect Transistor with A Tapered Gate Profile 审中-公开
    具有锥形栅极剖面的多栅极场效应晶体管

    公开(公告)号:US20130198695A1

    公开(公告)日:2013-08-01

    申请号:US13644398

    申请日:2012-10-04

    CPC classification number: H01L29/785 H01L29/42376

    Abstract: A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.

    Abstract translation: 一种多栅极场效应晶体管装置及其制造方法。 该装置包括源极端子,漏极端子和包括锥形栅极形状的栅极端子。 一种用于设计多栅极场效应晶体管的方法包括:设置具有锥形栅极剖面的源极端子,漏极端子和栅极端子,以在散热片的底部产生更宽的栅极宽度。

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