公开(公告)号：US20140201699A1

公开(公告)日：2014-07-17

申请号：US13741490

申请日：2013-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wilfried Ernest-August HAENSCH ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。

公开(公告)号：US20140131708A1

公开(公告)日：2014-05-15

申请号：US14158539

申请日：2014-01-17

Applicant: International Business Machines Corporation

Inventor： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC: H01L21/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract translation: 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US20130328016A1

公开(公告)日：2013-12-12

申请号：US13966427

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: G01N27/414

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

公开(公告)号：US20130230978A1

公开(公告)日：2013-09-05

申请号：US13859284

申请日：2013-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20130198695A1

公开(公告)日：2013-08-01

申请号：US13644398

申请日：2012-10-04

Applicant: International Business Machines Corporation

Inventor： Andres Bryant ,  Josephine B. Chang ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin

IPC: G06F17/50

CPC classification number: H01L29/785 ,  H01L29/42376

Abstract: A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.

Abstract translation: 一种多栅极场效应晶体管装置及其制造方法。 该装置包括源极端子，漏极端子和包括锥形栅极形状的栅极端子。 一种用于设计多栅极场效应晶体管的方法包括：设置具有锥形栅极剖面的源极端子，漏极端子和栅极端子，以在散热片的底部产生更宽的栅极宽度。

公开(公告)号：US10580894B2

公开(公告)日：2020-03-03

申请号：US15969444

申请日：2018-05-02

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

公开(公告)号：US10367072B2

公开(公告)日：2019-07-30

申请号：US15790604

申请日：2017-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/423 ,  H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/426 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/40 ,  H01L21/84 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/417

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US10083880B2

公开(公告)日：2018-09-25

申请号：US15494992

申请日：2017-04-24

Applicant: International Business Machines Corporation

Inventor： Chung-Hsun Lin ,  Yu-Shiang Lin ,  Shih-Hsien Lo ,  Joel A. Silberman

IPC: H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L21/3065 ,  H01L23/48 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

公开(公告)号：US09922831B2

公开(公告)日：2018-03-20

申请号：US15450508

申请日：2017-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/02

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US09570354B2

公开(公告)日：2017-02-14

申请号：US15075960

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.