公开(公告)号：US20090085152A1

公开(公告)日：2009-04-02

申请号：US11865079

申请日：2007-10-01

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L23/62 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

公开(公告)号：US07500208B2

公开(公告)日：2009-03-03

申请号：US11673369

申请日：2007-02-09

申请人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

发明人： Fen Chen ,  Jeffrey P. Gambino ,  Jason P. Gill ,  Baozhen Li ,  Timothy D. Sullivan

IPC分类号： G06F17/50 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

公开(公告)号：US07411135B2

公开(公告)日：2008-08-12

申请号：US10711885

申请日：2004-10-12

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01R12/04

CPC分类号： H01L23/544 ,  H01L22/24 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49227 ,  H01L2224/45099

摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.

摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。

公开(公告)号：US07405139B2

公开(公告)日：2008-07-29

申请号：US11462124

申请日：2006-08-03

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/322

CPC分类号： H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080146040A1

公开(公告)日：2008-06-19

申请号：US12041782

申请日：2008-03-04

申请人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/31

CPC分类号： C23C16/04 ,  C23C16/513 ,  H01J37/32366

摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.

摘要翻译： 一种用于执行该方法的方法和装置。 该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及 （iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质 在基板上的预定区域形成膜的反应。

公开(公告)号：US20080122037A1

公开(公告)日：2008-05-29

申请号：US11462124

申请日：2006-08-03

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Jerome B. Lasky ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L29/34 ,  H01L21/66

CPC分类号： H01L29/34 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。

公开(公告)号：US20080099877A1

公开(公告)日：2008-05-01

申请号：US11553176

申请日：2006-10-26

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5258 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。

公开(公告)号：US07361581B2

公开(公告)日：2008-04-22

申请号：US10904677

申请日：2004-11-23

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L21/44

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

摘要翻译： 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US07288475B2

公开(公告)日：2007-10-30

申请号：US11558959

申请日：2006-11-13

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

公开(公告)号：US07262451B2

公开(公告)日：2007-08-28

申请号：US10541660

申请日：2003-01-08

申请人： Jack A. Mandelman ,  Jeffrey P. Gambino ,  Geng Wang

发明人： Jack A. Mandelman ,  Jeffrey P. Gambino ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

摘要翻译： 半导体器件制造在同一衬底的应变层区域和无应变层的层中。 第一半导体器件，例如存储器单元，例如 在衬底的无应变层的区域中形成深沟槽存储单元。 在相同的衬底中选择性地形成应变层区域。 第二半导体器件（66,68,70），例如FET，例如， 一个MOSFET逻辑器件，形成在应变层区域中。