公开(公告)号：US20050141269A1

公开(公告)日：2005-06-30

申请号：US11066708

申请日：2005-02-24

申请人： Sheng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L27/115 ,  G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US20050127403A1

公开(公告)日：2005-06-16

申请号：US11031321

申请日：2005-01-05

申请人： Sheng Hsu

发明人： Sheng Hsu

IPC分类号： G11C13/02 ,  G11C7/04 ,  G11C7/06 ,  G11C7/14 ,  G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/10 ,  H01L31/0336

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/79

摘要： A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature dependent signal to compensate for the temperature variations of the resistance states of the memory resistors. The temperature dependent element can control the sensing signal supplied to the memory resistor so that the resistance states of the memory resistor are compensated against temperature variations. The temperature dependent element can control the reference signal supplied to the comparison circuit so that the output signal provided by the comparison circuit is compensated against temperature variations. The temperature dependent element is preferably made of the same material and process as the memory resistors.

公开(公告)号：US20050088898A1

公开(公告)日：2005-04-28

申请号：US10976596

申请日：2004-10-29

申请人： Sheng Hsu ,  Yoshi Ono

发明人： Sheng Hsu ,  Yoshi Ono

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L21/28194 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S438/975

摘要： Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

摘要翻译： 闪存单元设置有插入在浮置多晶硅栅极和控制栅极之间的高k材料。 在浮置多晶硅栅极和衬底之间插入隧道氧化物。 还提供了形成闪存单元的方法，包括在衬底上形成第一多晶硅层。 通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。 在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部 层。 然后可以使用CMP工艺将得到的结构平坦化。 然后可以在第一多晶硅层上沉积高k电介质层。 然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。 在图案化期间，蚀刻暴露的第二多晶硅层。 在完成去除第二多晶硅层时检测到蚀刻停止。 保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。 结合形成闪速存储器单元的过程，高k电介质层可以被图案化以允许形成非存储晶体管。

公开(公告)号：US20050054166A1

公开(公告)日：2005-03-10

申请号：US10659547

申请日：2003-09-09

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L27/105 ,  G11C11/22 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L29/78

CPC分类号： G11C11/22 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

公开(公告)号：US20070284575A1

公开(公告)日：2007-12-13

申请号：US11893402

申请日：2007-08-15

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

IPC分类号： H01L29/12

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

摘要翻译： 提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。 可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

公开(公告)号：US20070167008A1

公开(公告)日：2007-07-19

申请号：US11717818

申请日：2007-03-14

申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC分类号： H01L21/44

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

摘要翻译： 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。 通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。 一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。 使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

公开(公告)号：US20070111368A1

公开(公告)日：2007-05-17

申请号：US11280423

申请日：2005-11-16

申请人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

发明人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

IPC分类号： H01L51/40 ,  H01L21/00

CPC分类号： H01L51/4213 ,  B82Y10/00 ,  H01L51/0046 ,  H01L51/0048 ,  H01L51/4226 ,  H01L51/4233 ,  H01L51/441 ,  Y02E10/52 ,  Y02E10/549

摘要： A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

摘要翻译： 提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。 该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。 第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。 导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2，或铟的材料 氧化锡（ITO）。

公开(公告)号：US20070108502A1

公开(公告)日：2007-05-17

申请号：US11281955

申请日：2005-11-17

申请人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

发明人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  G11C16/349 ,  G11C16/3495 ,  G11C2216/08 ,  H01L29/15 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4925 ,  H01L29/66825

摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).

摘要翻译： 已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。 该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。 通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

公开(公告)号：US20070015330A1

公开(公告)日：2007-01-18

申请号：US11435669

申请日：2006-05-17

申请人： Tingkai Li ,  Sheng Hsu ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  David Evans

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US20070015328A1

公开(公告)日：2007-01-18

申请号：US11184660

申请日：2005-07-18

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.