公开(公告)号：US09489007B2

公开(公告)日：2016-11-08

申请号：US14448573

申请日：2014-07-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chang-Ting Chen

IPC: G06F1/08 ,  G11C17/16 ,  G11C17/18 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F1/08 ,  G06F1/10 ,  G11C7/222 ,  G11C7/225 ,  G11C17/16 ,  G11C17/18

Abstract: A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.

Abstract translation: 诸如集成电路存储器的集成电路上的可配置时钟电路可被配置为利用外部多相位时钟和外部单相时钟以与集成电路兼容的形式产生内部时钟信号。

公开(公告)号：US20160064921A1

公开(公告)日：2016-03-03

申请号：US14472520

申请日：2014-08-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC: H02H3/20 ,  H02H3/24 ,  G11C5/14

CPC classification number: H02H3/202 ,  G11C5/143 ,  H02H3/20 ,  H02H3/22 ,  H02H3/243 ,  H02H7/22

Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.

Abstract translation: 用于电压检测和保护的电路包括第一块，第一电压检测器，第二块和第二电压检测器。 第一块接收第一个电压源。 第一电压检测器检测第一电压源，并且当检测到第一电压供应电平在第一工作电压范围之外时产生第一检测信号。 第二块接收第二电压源。 第二电压检测器检测第二电压源，并且当检测到第二电压供应电平在第二工作电压范围之外时产生第二检测信号。 当监视第一和第二检测信号中的至少一个时，第一块在电路上执行保护操作。

公开(公告)号：US09275695B2

公开(公告)日：2016-03-01

申请号：US14506768

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/08 ,  G11C7/18 ,  G11C7/06

CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

公开(公告)号：US20160049925A1

公开(公告)日：2016-02-18

申请号：US14458936

申请日：2014-08-13

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC: H03K3/011 ,  H03K3/012

CPC classification number: H03K19/018521 ,  H03K19/00384

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

Abstract translation: 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 或者，输出缓冲器延迟是可变的。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且可以包括产生具有第一延迟的第一定时信号的第一延迟电路和产生具有第二延迟的第二定时信号的第二延迟电路， 与输出缓冲区延迟。

公开(公告)号：US09146809B2

公开(公告)日：2015-09-29

申请号：US14047418

申请日：2013-10-07

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Chang Huang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

Abstract translation: 提供一种操作存储用于相应数据的ECC的存储设备的方法。 该方法包括在第一程序操作期间写入扩展ECC，扩展ECC包括ECC和从ECC导出的扩展位。 该方法包括在第二程序操作期间以预定状态重写扩展ECC以指示第二程序操作。 该方法包括：在第一程序操作之前将ECC设置为初始ECC状态; 在第一程序操作期间，如果所计算的ECC等于预定状态，则计算ECC，将ECC改变为初始ECC状态; 并且如果ECC等于初始ECC状态，则将扩展位改变为初始值。 该方法包括读取包括扩展位的扩展ECC和用于相应数据的ECC，并且确定是否使用扩展ECC来启用ECC逻辑。

公开(公告)号：US09093172B2

公开(公告)日：2015-07-28

申请号：US14249270

申请日：2014-04-09

Applicant: Macronix International Co., Ltd.

Inventor： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

Abstract translation: 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。 该设备还包括用于从存储设备外部的源接收命令的命令接口。 该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。 泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

公开(公告)号：US20140160870A1

公开(公告)日：2014-06-12

申请号：US14183315

申请日：2014-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Nai-Ping Kuo ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Ming-Chih Hsieh

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/10 ,  G11C7/20

Abstract: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Abstract translation: 在所公开的技术中，存储器集成电路的器件识别码是可变的。 在一些情况下，多个设备识别码存储在存储器集成电路上，并且多个设备识别码选择数据被存储在存储器集成电路上。 设备识别码寄存器可以存储所选择的设备标识码。

公开(公告)号：US12131772B2

公开(公告)日：2024-10-29

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/00 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US10884956B2

公开(公告)日：2021-01-05

申请号：US15215439

申请日：2016-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F13/16 ,  G06F13/42

Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

公开(公告)号：US10680809B2

公开(公告)日：2020-06-09

申请号：US15984685

申请日：2018-05-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F11/30 ,  H04L9/08

Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.