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    3D memory structure and method for manufacturing the same
    52.
    发明授权
    3D memory structure and method for manufacturing the same 有权
    3D内存结构及其制造方法

    公开(公告)号：US09536573B2

    公开(公告)日：2017-01-03

    申请号：US14645446

    申请日：2015-03-12

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

    IPC: H01L29/49 ,  G11C5/06 ,  G11C8/10 ,  H01L23/528 ,  H01L21/768 ,  H01L27/115

    CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/11548 ,  H01L27/11575

    Abstract: A 3D memory structure and a method for manufactured the same are provided. The 3D memory structure comprises a plurality of strings, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of third conductive lines. The strings are disposed in parallel. The first conductive lines are disposed over the strings. Center regions of the first conductive lines are disposed perpendicular to the strings. The second conductive lines are disposed over the first conductive lines. The second conductive lines connect end regions of half of the first conductive lines. The third conductive lines are disposed over the second conductive lines. The third conductive lines connect end regions of the other half of the first conductive lines.

    Abstract translation: 提供了3D存储器结构及其制造方法。 3D存储器结构包括多个串，多个第一导线，多个第二导线和多个第三导线。 琴弦平行放置。 第一导线设置在弦上。 第一导线的中心区域垂直于弦线设置。 第二导线设置在第一导线上。 第二导线连接一半第一导线的端部区域。 第三导线设置在第二导线上。 第三导线连接第一导电线的另一半的端部区域。

    Antenna effect discharge circuit and manufacturing method
    53.
    发明授权
    Antenna effect discharge circuit and manufacturing method 有权
    天线效应放电电路及制造方法

    公开(公告)号：US09490249B2

    公开(公告)日：2016-11-08

    申请号：US14265635

    申请日：2014-04-30

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hang-Ting Lue ,  Teng-Hao Yeh

    IPC: H01L27/06 ,  H01L27/02 ,  H01L23/552 ,  H01L21/8238 ,  H01L27/115

    CPC classification number: H01L27/0629 ,  H01L21/823871 ,  H01L23/552 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An antenna effect discharge circuit is described for a device having patterned conductor layers, which may be exposed to charge inducing environments during a manufacturing process. The antenna effect discharge circuit has a terminal that is connected to a node on the device to be protected from charge accumulation and a gate, such as the gate of a field effect transistor in the circuit, and a terminal through which accumulated charge can be discharged to the substrate. A capacitor couples the gate in the antenna effect discharge circuit to the substrate. A voltage supply circuit is configured to provide voltage sufficient to bias the antenna effect discharge circuit in an off condition during operation of the device. A patterned conductor in the upper layer, and preferably the uppermost layer, of the device links the gate in the antenna effect discharge circuit to the voltage supply circuit.

    Abstract translation: 对于具有图案化导体层的器件描述了天线效应放电电路，其可能在制造过程中暴露于电荷诱导环境。 天线效应放电电路具有连接到要保护的装置上的节点免受电荷累积的端子和诸如电路中的场效应晶体管的栅极的栅极以及可以放电累积电荷的端子 到基底。 电容器将天线效应放电电路中的栅极耦合到衬底。 电压供给电路被配置为在设备的操作期间提供足以将天线效应放电电路偏置在关闭状态的电压。 该设备的上层，优选最上层的图案化导体将天线效应放电电路中的栅极连接到电压供应电路。

    Integrated circuit and operating method for the same
    56.
    发明授权
    Integrated circuit and operating method for the same 有权
    集成电路和操作方法相同

    公开(公告)号：US09245603B2

    公开(公告)日：2016-01-26

    申请号：US14058328

    申请日：2013-10-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

    IPC: G11C7/14 ,  H01L27/115

    CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

    Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

    Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

    MULTI-LAYER MEMORY ARRAY AND MANUFACTURING METHOD OF THE SAME
    57.
    发明申请
    MULTI-LAYER MEMORY ARRAY AND MANUFACTURING METHOD OF THE SAME 有权
    多层记忆阵列及其制造方法

    公开(公告)号：US20150357341A1

    公开(公告)日：2015-12-10

    申请号：US14296173

    申请日：2014-06-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

    IPC: H01L27/115 ,  H01L29/40

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

    Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

    Abstract translation: 存储器阵列包括沿着第一方向延伸的多个脊形多层堆叠，以及形成在所述多个脊形多层堆叠的顶部上的硬掩模层。 硬掩模层分别包括与多个脊形多层堆叠垂直对准的多个条带，沿着与第一方向正交的第二方向连接相邻条纹的多个桥，以及多个硬 通过多个桥和多个条之间的孔掩模。

    Array arrangement including carrier source
    58.
    发明授权
    Array arrangement including carrier source 有权
    阵列布置包括载波源

    公开(公告)号：US09076535B2

    公开(公告)日：2015-07-07

    申请号：US13936729

    申请日：2013-07-08

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yen-Hao Shih

    IPC: G11C16/04 ,  G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578

    Abstract: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions.

    Abstract translation: 为存储器提供了基于薄膜晶体管的存储器件中的电荷载体源。 电荷载流子源可以包括具有第一和第二端子的二极管。 经由第一开关耦合到位线的NAND串通过第二开关耦合到第二端，耦合到二极管的第一端。 分别可驱动的第一和第二电源线分别耦合到二极管的第一和第二端子。 包括耦合到第一和第二电源线的电路，其被配置为根据包括正向偏置条件和反向偏置条件的操作模式，以不同的偏置条件偏置第一和第二电源线。

    3-D IC device with enhanced contact area
    60.
    发明授权
    3-D IC device with enhanced contact area 有权
    具有增强接触面积的3-D IC器件

    公开(公告)号：US08981567B2

    公开(公告)日：2015-03-17

    申请号：US13948508

    申请日：2013-07-23

    Applicant: Macronix International Co., Ltd.

    Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

    IPC: H01L23/522 ,  H01L21/768 ,  H01L27/115 ,  H01L29/417 ,  H01L29/788 ,  H01L23/485

    CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

    Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

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