公开(公告)号：US08680613B2

公开(公告)日：2014-03-25

申请号：US13561300

申请日：2012-07-30

申请人： Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开描述了一种用于高电压半导体晶体管器件的端接结构。 终端结构由至少两个终端区域和身体层与设备的边缘之间的电断开组成。 第一区被配置成在设备内扩展电场。 第二区域被配置成平滑地将电场返回到设备的顶表面。 电气断开防止设备短路设备的边缘。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20130221430A1

公开(公告)日：2013-08-29

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US08247288B2

公开(公告)日：2012-08-21

申请号：US12947717

申请日：2010-11-16

申请人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L21/8242

CPC分类号： H01L23/5223 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0688 ,  H01L28/88 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.

摘要翻译： 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。

公开(公告)号：US20120205737A1

公开(公告)日：2012-08-16

申请号：US13456406

申请日：2012-04-26

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US08193580B2

公开(公告)日：2012-06-05

申请号：US12583191

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

摘要翻译： 半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。 非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。 另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。 源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。 另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。 第二顶栅电极比第二底源电极窄。

公开(公告)号：US20110147830A1

公开(公告)日：2011-06-23

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US20110039383A1

公开(公告)日：2011-02-17

申请号：US12583192

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8234

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

摘要翻译： 一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加 第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模， 金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

公开(公告)号：US09024375B2

公开(公告)日：2015-05-05

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/808 ,  H01L29/861 ,  H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US20140027840A1

公开(公告)日：2014-01-30

申请号：US13561300

申请日：2012-07-30

申请人： Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开描述了一种用于高电压半导体晶体管器件的端接结构。 终端结构由至少两个终端区域和身体层与设备的边缘之间的电断开组成。 第一区被配置成在设备内扩展电场。 第二区域被配置成平滑地将电场返回到设备的顶表面。 电气断开防止设备短路设备的边缘。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US08586414B2

公开(公告)日：2013-11-19

申请号：US12968159

申请日：2010-12-14

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kal Liu

IPC分类号： H01L21/00

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

摘要翻译： 半导体封装及其制造方法包括具有管芯焊盘的引线框架和设置在顶表面上的大致V形槽的源极引线。 设置在芯片焊盘上的半导体芯片。 连接到芯片的顶表面电极的金属板具有在V沟槽中终止的弯曲延伸部，与V沟槽侧壁中的至少一个接触。