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    Semiconductor memory device and information processor using the same
    53.
    发明授权
    Semiconductor memory device and information processor using the same 失效
    半导体存储器件和信息处理器使用它

    公开(公告)号：US6032229A

    公开(公告)日：2000-02-29

    申请号：US562187

    申请日：1995-11-22

    申请人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

    发明人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G11C11/401 ,  G11C11/407 ,  G06F13/00

    CPC分类号： G06F12/0855

    摘要： An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

    摘要翻译： 通过提高处理器和半导体存储器件的吞吐量来提供整体上具有高性能的信息处理器。 信息处理器包括具有用于临时保存数据的缓冲器的存储器和具有存储器接口部分的处理器，该存储器接口部分用于在确定数据是否被写入存储器之前控制存储器将数据传送到缓冲器，并将数据写入所述存储器 记忆确定写作后。 通过调整阅读和写入之间的数据交换，对半导体器件的数据写入和读取进行流水线化。 由于可以同时执行从存储器的读取和写入的数据传送定时，因此可以通过流水线的处理来执行读取处理和写入处理，并且可以提高吞吐量。

    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels
    54.
    发明授权
    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
    用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作

    公开(公告)号：US5646897A

    公开(公告)日：1997-07-08

    申请号：US426384

    申请日：1995-04-21

    申请人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    发明人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    IPC分类号： G11C7/10 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C7/1051 ,  G11C11/41 ,  G11C2029/5004 ,  G11C29/34

    摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

    摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

    Disk cartridge with a stop wall to engage a shutter plate projection and at least one support located between the stop wall and a cartridge side edge
    55.
    发明授权
    Disk cartridge with a stop wall to engage a shutter plate projection and at least one support located between the stop wall and a cartridge side edge 失效
    具有止动壁的磁盘盒，用于接合快门板突起和位于止动壁和盒侧边缘之间的至少一个支撑件

    公开(公告)号：US5627707A

    公开(公告)日：1997-05-06

    申请号：US523039

    申请日：1995-09-01

    申请人： Noboru Akiyama ,  Katsumi Kameda

    发明人： Noboru Akiyama ,  Katsumi Kameda

    IPC分类号： G11B23/03

    CPC分类号： G11B23/0303 ,  G11B23/0307 ,  G11B23/0308 ,  G11B23/0316

    摘要： A case supporting structure has four support pins provided in a disk player, a pair of the support pins having two small size locating pins on upper surfaces of the support pins, and four support seat places formed on the lower shell half. A pair of the support seat places respectively have a circular opening to receive one of the locating pins and an elliptic opening to receive loosely another locating pin. The support seat places on the lower shell half are of small smooth areas to be supported on the support pins.

    摘要翻译： 壳体支撑结构具有设置在盘播放器中的四个支撑销，一对支撑销在支撑销的上表面上具有两个小尺寸定位销，以及形成在下壳半部上的四个支撑座位。 一对支撑座位分别具有圆形开口以接收一个定位销和一个椭圆形开口以松动地接收另一个定位销。 支撑座位于下半壳体上的小平滑区域被支撑在支撑销上。

    Automatic pattern synchronizing circuit of an error detector
    56.
    发明授权
    Automatic pattern synchronizing circuit of an error detector 失效
    错误检测器的自动图案同步电路

    公开(公告)号：US5463639A

    公开(公告)日：1995-10-31

    申请号：US234043

    申请日：1994-04-28

    申请人： Tetsuya Koishi ,  Noboru Akiyama ,  Yasuto Kumai

    发明人： Tetsuya Koishi ,  Noboru Akiyama ,  Yasuto Kumai

    IPC分类号： G06F11/24 ,  G01R31/28

    CPC分类号： G06F11/24

    摘要： An automatic pattern synchronizing circuit re-times the phase differences between clocks, thereby adjusting test pattern outputs from a device under test. The automatic pattern synchronizing circuit includes a reference voltage generator for providing a threshold voltage, a comparator for converting an input signal into a rectangular signal, a flip-flop, a pattern-counter part for counting a signal from the flip-flop and a control part for setting the threshold voltage in the comparator. The automatic pattern synchronizing circuit automatically synchronizes voltage patterns. In particular, the high and low voltage levels of the input waveform are automatically measured and the optimum threshold voltage is automatically set.

    摘要翻译： 自动图案同步电路对时钟之间的相位差进行重新计时，从而调整来自被测器件的测试图案输出。 自动图案同步电路包括用于提供阈值电压的参考电压发生器，用于将输入信号转换为矩形信号的比较器，触发器，用于对来自触发器的信号进行计数的图形计数器部分和控制 用于设置比较器中的阈值电压的部分。 自动模式同步电路自动同步电压模式。 特别地，自动测量输入波形的高低电压电平，并自动设置最佳阈值电压。

    Logic analyzer
    59.
    发明授权
    Logic analyzer 失效
    逻辑分析仪

    公开(公告)号：US4701918A

    公开(公告)日：1987-10-20

    申请号：US737467

    申请日：1985-05-24

    申请人： Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

    发明人： Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

    IPC分类号： G01R31/3177 ,  G06F11/25 ,  G01R31/28 ,  G06F11/00

    CPC分类号： G01R31/3177 ,  G06F11/25

    摘要： A logic analyzer applies test pattern signals from a pattern generator to a circuit under test and sequentially reads logic outputs into a memory. The output from the circuit under test when it reaches a predetermined logic state is input as an external control signal into the logic analyzer. A change command is generated from the pattern generator in relation to the generation of the test pattern signal. When the change command and the external control signal are obtained at the same time, and flow of the generation of the test pattern signals is changed to a predetermined flow.

    摘要翻译： 逻辑分析仪将来自模式发生器的测试模式信号应用于被测电路，并将逻辑输出顺序读入存储器。 当达到预定逻辑状态时，被测电路的输出作为外部控制信号输入到逻辑分析仪中。 相对于测试图形信号的生成，从图案生成器生成变更命令。 当同时获得改变命令和外部控制信号时，将测试图形信号的产生流程改变为预定流量。