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公开(公告)号：US09569396B2
公开(公告)日：2017-02-14
申请号：US14931652
申请日：2015-11-03
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
IPC: G06F3/00 , G06F13/42 , H04L1/00 , H04L1/20 , H04L1/24 , H04L5/14 , G06F13/38 , G06F13/40 , H04L25/02
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。
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公开(公告)号：US20160373277A1
公开(公告)日：2016-12-22
申请号：US15178493
申请日：2016-06-09
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
IPC: H04L25/03
CPC classification number: H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号被调整为第一个α值以导出第一个调整的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。
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53.发明申请INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR 有权具有包括注射锁定振荡器的时钟电路的集成电路公开(公告)号：US20160226504A1
公开(公告)日：2016-08-04
申请号：US14990443
申请日：2016-01-07
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。
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公开(公告)号：US09304579B2
公开(公告)日：2016-04-05
申请号：US14798050
申请日：2015-07-13
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Jared L. Zerbe , Brian S. Leibowitz
IPC: G11C5/14 , G06F1/32 , G11C11/4072 , G11C11/4076 , G11C7/22 , G06F3/06 , G11C7/04
CPC classification number: G06F1/3275 , G06F1/324 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F2213/0038 , G11C5/14 , G11C5/148 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C2207/2227 , G11C2207/2254
Abstract: A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.
Abstract translation: 存储器控制器转换到低功率模式，其中禁用以第一命令信令频率将存储器访问命令发送到存储器设备所需的主动模式资源。 存储器控制器在其中重新启用活动模式资源的过渡间隔期间使用替代信令资源向存储器设备发送第一存储器访问命令。
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55.发明申请HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION 有权高速信号系统和方法具有适应性，连续时间均衡公开(公告)号：US20150078430A1
公开(公告)日：2015-03-19
申请号：US14552598
申请日：2014-11-25
Applicant: RAMBUS INC.
Inventor： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
CPC classification number: H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
Abstract translation: 接收机包括连续时间均衡器，判决反馈均衡器（DFE），数据和误差采样逻辑以及适配引擎。 接收机通过基于第一后视标ISI的测量建立连续时间均衡器的适当均衡设置来校正与最新数据符号（第一后光标ISI）相关联的符号间干扰（ISI）。
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Patent Agency Ranking
56.发明申请INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR 有权具有包括注射锁定振荡器的时钟电路的集成电路公开(公告)号：US20140333386A1
公开(公告)日：2014-11-13
申请号：US14444669
申请日：2014-07-28
Applicant: Rambus Inc.
Inventor： Marko Aleksic , Brian S. Leibowitz
IPC: H03L7/099
CPC classification number: H03L7/24 , H03K5/26 , H03K2005/00286 , H03L7/081 , H03L7/099 , H03L7/0995
Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。
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公开(公告)号：US08811553B2
公开(公告)日：2014-08-19
申请号：US13932561
申请日：2013-07-01
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
CPC classification number: H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
Abstract: A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.
Abstract translation: 设备实现基于边缘的部分响应判决反馈均衡的数据接收。 在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。 抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。 时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。
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公开(公告)号：US12142348B2
公开(公告)日：2024-11-12
申请号：US18460413
申请日：2023-09-01
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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公开(公告)号：US11886375B2
公开(公告)日：2024-01-30
申请号：US17751480
申请日：2022-05-23
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D30/50
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
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公开(公告)号：US11783879B2
公开(公告)日：2023-10-10
申请号：US17531151
申请日：2021-11-19
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
CPC classification number: G11C8/12 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1012 , G11C7/1045 , G11C8/18 , H01L24/49 , H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48095 , H01L2224/48227 , H01L2224/48471 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2225/0651 , H01L2924/00012 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/48095 , H01L2924/00014 , H01L2924/00014 , H01L2224/45099 , H01L2224/49171 , H01L2224/48227 , H01L2924/00 , H01L2224/49171 , H01L2224/48471 , H01L2924/00 , H01L2224/49171 , H01L2224/49433 , H01L2924/00 , H01L2924/181 , H01L2924/00012
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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