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106 条记录 (耗时 0.026 秒)

    NiSi metal gate stacks using a boron-trap
    52.
    发明申请
    NiSi metal gate stacks using a boron-trap 有权
    NiSi金属栅堆叠使用硼陷阱

    公开(公告)号：US20050130366A1

    公开(公告)日：2005-06-16

    申请号：US10734768

    申请日：2003-12-12

    申请人： Jiong-Ping Lu

    发明人： Jiong-Ping Lu

    IPC分类号： H01L21/28 ,  H01L21/8238

    CPC分类号： H01L21/28097 ,  H01L21/823835

    摘要： A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.

    摘要翻译： 在退火期间使用覆盖层（118）以形成完全硅化的NiSi栅电极（120）。 覆盖层（118）包括对硼具有亲和性的材料，例如TiN。 覆盖层（118）用作硼阱，其降低PMOS晶体管的界面硼浓度，而不降低NMOS晶体管的界面砷浓度。

    Method for improved cu electroplating in integrated circuit fabrication
    54.
    发明授权
    Method for improved cu electroplating in integrated circuit fabrication 有权
    在集成电路制造中改进铜电镀的方法

    公开(公告)号：US06784104B2

    公开(公告)日：2004-08-31

    申请号：US10194592

    申请日：2002-07-12

    申请人： Qing-Tang Jiang ,  Jiong-Ping Lu

    发明人： Qing-Tang Jiang ,  Jiong-Ping Lu

    IPC分类号： H10L214763

    CPC分类号： H01L21/76888 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76886

    摘要： The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.

    摘要翻译： 铜的电镀是在集成电路上形成铜线的领先技术。 在铜电镀工艺中，半导体晶片的表面作为阴极施加负电位至半导体晶片。 阳极将部分或全部由铜形成。 阳极和半导体都将暴露于包含铜电解质的溶液中。 通过将铜电解质溶液的温度降低到25℃以下，自退火晶粒生长速率将会降低铜线的最终电阻。

    System for reducing silicon-consumption through selective deposition
    55.
    发明授权
    System for reducing silicon-consumption through selective deposition 有权
    通过选择性沉积降低硅消耗的系统

    公开(公告)号：US06630394B2

    公开(公告)日：2003-10-07

    申请号：US10131162

    申请日：2002-04-24

    申请人： Jiong-Ping Lu ,  Jin Zhao ,  Yuqing Xu

    发明人： Jiong-Ping Lu ,  Jin Zhao ,  Yuqing Xu

    IPC分类号： H01L21336

    CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7834

    摘要： Disclosed is a system for fabricating a semiconductor device (100). A layer of cobalt (32) is deposited onto a silicon region (104, 106, 108) and annealed to form a cobalt silicide layer (118, 120, 122). Silicon layers (124, 126, 128) are selectively deposited onto the cobalt silicide layers (118, 120, 122). The semiconductor device (100) is annealed to form disilicide layers (130, 132, 134) from the cobalt silicide layers (118, 120, 122) and the silicon contained in silicon regions (104, 106, 108) and silicon layers (124, 126, 128).

    摘要翻译： 公开了一种用于制造半导体器件（100）的系统。 一层钴（32）沉积在硅区（104,106,108）上并退火以形成硅化钴层（118,120,122）。 硅层（124,126,128）被选择性地沉积在钴硅化物层（118,120,122）上。 半导体器件（100）被退火以形成来自硅化钴层（118,120,122）的二硅化物层（130,132,134）和包含在硅区域（104,106,108）和硅层（124）中的硅 ，126,128）。

    Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process
    56.
    发明授权
    Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process 有权
    在钨金属化过程中等离子体增强的成核层的化学气相沉积

    公开(公告)号：US06451677B1

    公开(公告)日：2002-09-17

    申请号：US09255489

    申请日：1999-02-23

    申请人： Jiong-Ping Lu ,  Boyang Lin ,  Wei-Yung Hsu

    发明人： Jiong-Ping Lu ,  Boyang Lin ,  Wei-Yung Hsu

    IPC分类号： H01L213205

    CPC分类号： H01L21/76876 ,  H01L21/28556 ,  H01L21/76843

    摘要： An embodiment of the instant invention is a method of fabricating an electronic device formed over a semiconductor substrate and having a conductive feature comprised of tungsten, the method comprising the steps of: forming a nucleation layer over the semiconductor substrate by introducing a combination of WF6, H2 and a plasma; and forming a tungsten layer on the nucleation layer by means of chemical vapor deposition. In an alternative embodiment, an insulating layer is formed on the substrate and situated between the nucleation layer and the substrate. Preferably, this embodiment additionally includes the step of forming a nitrogen-containing layer under the nucleation layer by introducing a combination of WF6, N2, H2, and a plasma. The conductive feature is, preferably, a conductive gate structure, and the insulating layer is, preferably, comprised of: an oxide, a nitride, an insulating material with a dielectric constant substantially higher than that of an oxide, and any combination thereof.

    摘要翻译： 本发明的一个实施例是一种制造形成在半导体衬底上并且具有由钨构成的导电特征的电子器件的方法，该方法包括以下步骤：通过引入WF6的组合形成半导体衬底上的成核层， H2和等离子体; 并通过化学气相沉积在成核层上形成钨层。 在替代实施例中，绝缘层形成在衬底上并且位于成核层和衬底之间。 优选地，该实施方案另外包括通过引入WF 6，N 2，H 2和等离子体的组合在成核层下形成含氮层的步骤。 导电特征优选地是导电栅极结构，并且绝缘层优选地包括：氧化物，氮化物，具有显着高于氧化物的介电常数的绝缘材料及其任何组合。

    Process for depositing thin films containing titanium and nitrogen
    57.
    发明授权
    Process for depositing thin films containing titanium and nitrogen 失效
    用于沉积含有钛和氮的薄膜的方法

    公开(公告)号：US06365517B1

    公开(公告)日：2002-04-02

    申请号：US09010373

    申请日：1998-01-21

    申请人： Jiong-Ping Lu ,  Ming-Jang Hwang

    发明人： Jiong-Ping Lu ,  Ming-Jang Hwang

    IPC分类号： H01L21443

    CPC分类号： H01L21/76843 ,  C23C16/30 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28061 ,  H01L21/28556 ,  H01L21/76856 ,  H01L27/1085 ,  H01L28/75 ,  H01L28/82 ,  H01L28/90

    摘要： An embodiment of the instant invention is a method of depositing a TiN-based film over a semiconductor wafer, the method comprising the steps of: substantially simultaneously subjecting the semiconductor wafer to TiCl4, H2, and N2; and subjecting the semiconductor wafer to a plasma, such that the combination of the TiCl4, H2, and N2 and the plasma cause the deposition of a TiN based film to form over the semiconductor wafer. Another embodiment of the instant invention involves additionally subjecting the semiconductor wafer to SiH4 so as to form a TiSixNy film over the semiconductor wafer. Another embodiment of the instant invention involves additionally subjecting the semiconductor wafer to B2H6 so as to form a TiNxBy layer over the semiconductor wafer.

    摘要翻译： 本发明的一个实施方案是在半导体晶片上沉积TiN基膜的方法，该方法包括以下步骤：基本上同时使半导体晶片经历TiCl 4，H 2和N 2; 并且使半导体晶片经受等离子体，使得TiCl 4，H 2和N 2与等离子体的组合导致在半导体晶片上形成TiN基膜的沉积。 本发明的另一实施例涉及另外对半导体晶片进行SiH4的处理，以便在半导体晶片上形成TiSixNy膜。 本发明的另一实施例涉及另外对半导体晶片进行B2H6的处理，以在半导体晶片上形成TiNxBy层。

    FUSI integration method using SOG as a sacrificial planarization layer
    60.
    发明授权
    FUSI integration method using SOG as a sacrificial planarization layer 有权
    使用SOG作为牺牲平坦化层的FUSI积分方法

    公开(公告)号：US07732313B2

    公开(公告)日：2010-06-08

    申请号：US12348660

    申请日：2009-01-05

    申请人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    发明人： Jiong-Ping Lu ,  Yaw S. Obeng ,  Ping Jiang ,  Joe G. Tran

    IPC分类号： H01L21/44

    CPC分类号： H01L21/31055 ,  H01L21/28097 ,  H01L21/32134 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

    摘要翻译： 一种制造晶体管20的方法，其包括使用过渡金属氮化物层200和/或SOG层220来保护源极/漏极区域60在栅电极90的硅化期间不被硅化。SOG层210被平坦化以暴露 在栅极硅化处理之前的过渡金属氮化物层200或栅电极93。 如果使用过渡金属氮化物层200，则在栅电极90完全硅化之前，从栅电极93的顶部去除它。