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    Low-supply-voltage nonvolatile memory device with voltage boosting
    51.
    发明授权
    Low-supply-voltage nonvolatile memory device with voltage boosting 失效
    具有升压功能的低电压非易失性存储器件

    公开(公告)号：US5903498A

    公开(公告)日：1999-05-11

    申请号：US877927

    申请日：1997-06-18

    申请人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

    发明人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

    IPC分类号： G11C16/08 ,  G11C7/00

    CPC分类号： G11C16/08

    摘要： The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.

    摘要翻译： 存储器件具有多个本地升压电路，每个局部升压电路各自连接到存储器阵列的扇区，并且每个具有控制电路，至少相应的升压电容器和相应的驱动电路。 每个驱动电路仅在读取模式下被启用，在接收到地址转换检测信号和扇区使能信号时，用于读取形成相应扇区的一部分的存储器单元。 升压电压仅提供给行解码器的最终反相器。 钳位二极管限制升压电压，以防止连接到非寻址字线的最终逆变器的PMOS晶体管的不期望的直接偏置。 因此，过电压仅在必要时在当地提供。

    INTERFACE BOARD OF A TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES AND CORRESPONDING PROBE HEAD
    53.
    发明申请
    INTERFACE BOARD OF A TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES AND CORRESPONDING PROBE HEAD 有权
    用于电子设备测试设备和相关探头的测试头接口板

    公开(公告)号：US20140015560A1

    公开(公告)日：2014-01-16

    申请号：US13548004

    申请日：2012-07-12

    申请人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    发明人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    IPC分类号： G01R1/073

    CPC分类号： G01R1/07378

    摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

    摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。

    ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES
    55.
    发明申请
    ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES 有权
    在多个存储器件中增加存储容量的错误校正代码

    公开(公告)号：US20100318877A1

    公开(公告)日：2010-12-16

    申请号：US12482400

    申请日：2009-06-10

    申请人： Paolo Amato ,  Giovanni Campardo

    发明人： Paolo Amato ,  Giovanni Campardo

    IPC分类号： H03M13/29 ,  H03M13/11 ,  G06F11/10

    CPC分类号： H03M13/05 ,  G11C2029/0411 ,  H03M13/15 ,  H03M13/152 ,  H03M13/256 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2933 ,  H03M13/2936 ,  H03M13/41

    摘要： Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.

    摘要翻译： 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。

    MULTI CHIP ELECTRONIC SYSTEM
    57.
    发明申请
    MULTI CHIP ELECTRONIC SYSTEM 有权
    多芯片电子系统

    公开(公告)号：US20080278923A1

    公开(公告)日：2008-11-13

    申请号：US12116852

    申请日：2008-05-07

    申请人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    发明人： Aldo Losavio ,  Giovanni Campardo ,  Stefano Ricciardi

    IPC分类号： H05K1/14

    CPC分类号： H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

    摘要翻译： 一种适于执行相应功能并且至少包括第一子系统和第二子系统的电子系统，所述第一子系统和所述第二子系统通过多个电连接可操作地彼此耦合以执行所述系统的功能，其中 第一子系统和第二子系统分别集成在第一材料芯片上并且在第二材料芯片上，多个电连接包括形成在第一和第二芯片中的至少一个芯片中的多个导电通孔，并且适于形成 当第一和第二芯片叠加时相应的多个芯片间电连接。

    Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors
    59.
    发明授权
    Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors 失效
    使用源极线开关晶体管编程非易失性闪存EEPROM存储器阵列的方法

    公开(公告)号：US5633822A

    公开(公告)日：1997-05-27

    申请号：US458346

    申请日：1995-06-02

    申请人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

    发明人： Giovanni Campardo ,  Giuseppe Crisenza ,  Marco Dallabora

    IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C16/02

    CPC分类号： G11C16/04 ,  G11C16/0416 ,  G11C16/30

    摘要： A method for writing cells in a memory which reduces errors caused by depleted memory array cells being turned on even when not selected. In the method, nonselected bit lines and nonselected word lines are biased so that the threshold voltage of the nonselected cells increases. In particular, the nonselected bit lines are left floating and the nonselected word lines are set to a zero voltage. Appropriate potentials are applied to the selected word line, selected bit line, and selected source line in order to program the selected cell.

    摘要翻译： 一种用于将存储器中的单元写入的方法，其减少由耗尽的存储器阵列单元导致的错误，即使在未选择的情况下也被导通。 在该方法中，非选择位线和非选择字线被偏置，使得非选择单元的阈值电压增加。 特别地，非选定的位线保持浮动，并且非选择的字线被设置为零电压。 适当的电位被施加到所选择的字线，所选位线和所选择的源极线以便对所选择的单元进行编程。

    Interface board of a testing head for a test equipment of electronic devices and corresponding probe head
    60.
    发明授权
    Interface board of a testing head for a test equipment of electronic devices and corresponding probe head 有权
    用于电子设备测试设备和相应探头的测试头接口板

    公开(公告)号：US09069015B2

    公开(公告)日：2015-06-30

    申请号：US13548004

    申请日：2012-07-12

    申请人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    发明人： Giovanni Campardo ,  Flavio Maggioni ,  Riccardo Liberini

    IPC分类号： G01R1/073

    CPC分类号： G01R1/07378

    摘要： An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

    摘要翻译： 描述了用于电子设备的测试设备的测试头的接口板。 测试头包括多个接触探针，每个接触探针具有至少一个适于邻接待测试装置的接触垫的接触尖端，以及用于与测试设备的板连接的接触元件。 适当地，接口板包括衬底和容纳在该衬底的第一表面上的至少一个重定向模具和从该衬底的与第一表面相对的第二表面突出的多个接触针。 重定向管芯包括至少一个半导体衬底，其中至少第一多个接触焊盘被实现，适于接触测试头的接触探针的接触元件，接触针适于接触该板。