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    PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
    51.
    发明申请
    PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY 审中-公开

    公开(公告)号：US20200371877A1

    公开(公告)日：2020-11-26

    申请号：US16874435

    申请日：2020-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

    ZERO CYCLE CLOCK INVALIDATE OPERATION
    53.
    发明申请
    ZERO CYCLE CLOCK INVALIDATE OPERATION 审中-公开
    零周期无效操作

    公开(公告)号：US20160026569A1

    公开(公告)日：2016-01-28

    申请号：US14875801

    申请日：2015-10-06

    Applicant: Texas Instruments Incorporated

    Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

    Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be treated as a cache miss to ensure that the requesting CPU will receive valid data.

    Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并且映射到块无效操作的地址范围内的访问将被视为缓存未命中，以确保请求的CPU将接收有效数据 。

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    55.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20250103502A1

    公开(公告)日：2025-03-27

    申请号：US18976474

    申请日：2024-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

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