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51.发明授权Method for forming a thick-film resistor and thick-film resistor formed thereby 失效用于形成由此形成的厚膜电阻器和厚膜电阻器的方法公开(公告)号：US06171921B2
公开(公告)日：2001-01-09
申请号：US09093007
申请日：1998-06-05
IPC分类号： B05D512
CPC分类号： H05K1/167 , H01C17/003 , H01C17/065 , H05K1/095 , H05K3/0023 , H05K3/4644 , H05K2201/09509 , H05K2203/0568
摘要： A process for forming a thick-film resistor whose dimensions can be accurately obtained, thereby yielding a precise resistance value. The method includes providing on a substrate a photoimageable layer that preferably forms a permanent dielectric layer of a multilayer structure. An opening is photodefined in the surface of the photoimageable layer, and then overfilled with an electrically-resistive material to form a resistive mass having an excess portion that lies on the surface of the photoimageable layer surrounding the opening. Following curing which causes the surface of the resistive material to become recessed below the surface of the photoimageable layer, the excess portion of the resistive mass is removed, preferably by abrading or a similar operation, such that the lateral dimensions of the resistive mass are determined by the lateral dimensions of the opening in the photoimageable layer. Thereafter, subsequent processing is preformed to include the photoimageable layer as a permanent photoimageable layer of a circuit board, with the resistive mass and appropriate terminations forming a resistor in the permanent photoimageable layer.
摘要翻译： 一种用于形成可以精确获得尺寸的厚膜电阻器的方法，从而产生精确的电阻值。 该方法包括在基底上提供优选形成多层结构的永久介电层的可光成像层。 在光致成像层的表面中光刻限定开口，然后用电阻材料过满，以形成具有位于围绕开口的可光成象层的表面上的多余部分的电阻质量。 在固化之后，电阻材料的表面在可光成像层的表面下凹陷，电阻质量块的过剩部分优选通过研磨或类似的操作被去除，使得电阻质量的横向尺寸被确定 通过可光成像层中的开口的横向尺寸。 此后，进行后续处理，以将可光成像层作为电路板的永久可光成像层，其中电阻质量和合适的端接在永久可光成像层中形成电阻器。
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52.发明授权公开(公告)号：US09253416B2
公开(公告)日：2016-02-02
申请号：US12142297
申请日：2008-06-19
申请人： Gregory J. Dunn , Terance B. Blake
发明人： Gregory J. Dunn , Terance B. Blake
CPC分类号： H04N5/272 , G06T11/60 , H04M1/72544 , H04M2250/12 , H04M2250/52 , H04M2250/62 , H04N5/232 , H04N5/2621 , H04N2007/145
摘要： A device and method of background substitution are disclosed. One or more cameras in a mobile device obtain a depth image. A processor in or external to the device segments the foreground from the background of the image. The original background is removed and a stored background image or video is substituted in place of the original background. The substituted background is altered dependent on the attitude and motion of the device, which is sensed by one or more sensors in the device. A portion of the stored background selected as the substitute background varies in correspondence with the device movement.
摘要翻译： 公开了背景替换的装置和方法。 移动设备中的一个或多个摄像机获得深度图像。 设备中或外部的处理器从图像的背景分割前景。 原始背景被删除，存储的背景图像或视频代替原始背景。 取代的背景取决于装置的姿态和运动，其由装置中的一个或多个传感器感测到。 选择作为替代背景的存储背景的一部分根据设备移动而变化。
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公开(公告)号：US20120162857A1
公开(公告)日：2012-06-28
申请号：US13409424
申请日：2012-03-01
CPC分类号： H05K1/162 , H01G9/012 , H01G9/042 , H01G9/045 , H01G9/15 , H05K3/429 , H05K2201/0329 , H05K2201/0355 , H05K2201/09509 , H05K2201/09763 , H05K2201/09909 , H05K2203/0315 , Y10T29/417 , Y10T29/435
摘要： A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
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54.发明申请Method and Apparatus to Facilitate Removing a Visual Distraction From an Image Being Captured 审中-公开方法和装置，有助于从被捕获的图像中去除视觉分心公开(公告)号：US20100054632A1
公开(公告)日：2010-03-04
申请号：US12202840
申请日：2008-09-02
IPC分类号： G06K9/03
CPC分类号： G06T11/001
摘要： One provides (101) a captured image of a real-world setting that comprises both target content and at least one visual distraction. One also provides (102), via a display, information regarding selectable elements of the captured image as a function of the relative positions (such as relative depth) of the selectable elements with respect to one another. An end user (via an end-user interface) can select (103) at least one visual distraction as a selected element. Additional image content from the real-world setting can then be accumulated (105) for a portion of the target content as corresponds to the selected element. This additional image content is then aggregated (106) with previously obtained image content for the target content to facilitate the provision of an image of the real-world setting that comprises the target content in the absence of the at least one visual distraction.
摘要翻译： 一个提供（101）包括目标内容和至少一个视觉分心的现实设置的捕获图像。 还可以通过显示器提供关于可选择元素相对于彼此的相对位置（例如相对深度）的函数关于所捕获图像的可选元素的信息（102）（102）。 最终用户（通过最终用户界面）可以选择（103）至少一个视觉分心作为所选择的元素。 然后可以对与所选元素相对应的目标内容的一部分累积来自真实世界设置的附加图像内容（105）。 然后将该附加图像内容与先前获得的用于目标内容的图像内容聚合（106），以便于在没有至少一个视觉分心的情况下提供包括目标内容的真实世界设置的图像。
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公开(公告)号：US07528788B2
公开(公告)日：2009-05-05
申请号：US12174960
申请日：2008-07-17
IPC分类号： H01Q3/40
CPC分类号： H01Q15/006 , H05K1/116 , H05K1/162 , H05K1/165 , H05K3/429 , H05K3/4602 , H05K3/4688 , H05K2201/0187 , H05K2201/0715 , H05K2201/09509 , H05K2201/09609
摘要： A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).
摘要翻译： 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。
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公开(公告)号：US20080272982A1
公开(公告)日：2008-11-06
申请号：US12174960
申请日：2008-07-17
IPC分类号： H01Q15/24
CPC分类号： H01Q15/006 , H05K1/116 , H05K1/162 , H05K1/165 , H05K3/429 , H05K3/4602 , H05K3/4688 , H05K2201/0187 , H05K2201/0715 , H05K2201/09509 , H05K2201/09609
摘要： A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).
摘要翻译： 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。
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57.发明授权Method for forming multi-layer embedded capacitors on a printed circuit board 失效在印刷电路板上形成多层嵌入式电容器的方法公开(公告)号：US07444727B2
公开(公告)日：2008-11-04
申请号：US11276688
申请日：2006-03-10
申请人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
发明人： Jovica Savic , Remy J. Chelini , Gregory J. Dunn
CPC分类号： H01G4/33 , H01G4/12 , H05K1/162 , H05K3/0044 , H05K2201/0175 , H05K2201/0187 , H05K2201/0195 , H05K2201/0209 , H05K2201/09509 , H05K2203/025 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.
摘要翻译： 公开了一种在印刷电路板上形成嵌入式电容器的方法。 通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。 另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。 在第二电介质层的顶部形成第三电极。 通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。
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公开(公告)号：US20080121420A1
公开(公告)日：2008-05-29
申请号：US11557711
申请日：2006-11-08
IPC分类号： H05K1/00
CPC分类号： H05K3/427 , H05K1/115 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/0047 , H05K3/4602 , H05K2201/0394 , H05K2201/0959 , H05K2201/0969 , H05K2201/097 , H05K2201/09845 , H05K2203/1476
摘要： Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.
摘要翻译： 通过在每侧具有金属层的中心芯的一侧层叠电介质层，在多层印刷电路板中形成封闭的通孔。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。
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公开(公告)号：US20080119041A1
公开(公告)日：2008-05-22
申请号：US11557690
申请日：2006-11-08
IPC分类号： H05K3/30 , H01L21/4763
CPC分类号： H05K3/427 , H05K1/115 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/0047 , H05K3/4602 , H05K3/4652 , H05K2201/0394 , H05K2201/0959 , H05K2201/0969 , H05K2201/097 , H05K2201/09845 , H05K2203/1476 , Y10T29/49165
摘要： A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.
摘要翻译： 一种在多层印刷电路板中形成封闭通孔的方法。 电介质层被层叠在每侧具有金属层的中心芯的一侧。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。
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公开(公告)号：US07193838B2
公开(公告)日：2007-03-20
申请号：US10744695
申请日：2003-12-23
申请人： Gregory J. Dunn , Remy J. Chilini , Robert T. Croswell , Timothy B. Dean , Claudia V. Gamboa , Jovica Savic
发明人： Gregory J. Dunn , Remy J. Chilini , Robert T. Croswell , Timothy B. Dean , Claudia V. Gamboa , Jovica Savic
IPC分类号： H01G4/30
CPC分类号： H05K1/162 , H05K3/025 , H05K3/429 , H05K2201/0175 , H05K2201/0355 , H05K2201/09309 , H05K2201/09509 , H05K2201/09718
摘要： A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).
摘要翻译： 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。
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