公开(公告)号：US08644086B2

公开(公告)日：2014-02-04

申请号：US13137849

申请日：2011-09-16

申请人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

发明人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

IPC分类号： G11C7/00

CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.

摘要翻译： 半导体器件包括多个第一芯片，控制第一芯片的第二芯片和连接第一芯片和第二芯片的内部布线。 第一个芯片包括：一个光学保险丝; 第一锁存电路，其保存关于所述光学保险丝的信息; 第二锁存电路，其保存关于电熔丝的信息，所述信息通过所述内部布线从所述第二芯片提供; 以及选择电路，其选择保留在第一和第二锁存电路中的任一个中的信息。 从所选择的信息生成冗余确定信号。 电熔丝的信息通过内部布线从第二芯片传送到第一芯片。

公开(公告)号：US08593899B2

公开(公告)日：2013-11-26

申请号：US12929967

申请日：2011-02-28

申请人： Akira Ide

发明人： Akira Ide

IPC分类号： G11C8/00

CPC分类号： G11C8/06 ,  G11C5/025 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.

摘要翻译： 为了提高包括多个存储器芯片的半导体存储器的访问效率。 基于与行命令同步地接收的层地址，存储体地址和行地址以及与列命令同步地接收的层地址，存储体地址和列地址，由行选择的存储单元 访问由由芯片地址选择的核心芯片中包含的存储体地址选择的存储体中的地址和列地址。 这可以增加控制器可识别的存储体的数量，从而提高包括多个存储器芯片的半导体器件的存储器访问效率。

公开(公告)号：US08350389B2

公开(公告)日：2013-01-08

申请号：US12923789

申请日：2010-10-07

申请人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

发明人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

摘要翻译： 半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。 芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。 贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。 在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。 因此，可以确保更大的寄生电容。

公开(公告)号：US20120075944A1

公开(公告)日：2012-03-29

申请号：US13200649

申请日：2011-09-28

申请人： Akira Ide ,  Hiroki Ichikawa

发明人： Akira Ide ,  Hiroki Ichikawa

IPC分类号： G11C29/04 ,  H01L21/00

CPC分类号： G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/5606

摘要： A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.

摘要翻译： 按顺序测试多个存储单元。 每次通过测试检测到有缺陷的存储单元时，基于多个有缺陷的存储单元之间的相对布置关系来更新错误模式信息，并且基于多个缺陷存储器单元的至少一部分的地址来更新错误地址信息 记忆细胞 根据本发明，可以显着降低分析存储器的存储容量。 这允许在半导体器件中实现分析存储器本身，在这种情况下外部测试器不需要包括分析存储器。

公开(公告)号：US20120069685A1

公开(公告)日：2012-03-22

申请号：US13137849

申请日：2011-09-16

申请人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

发明人： Akira Ide ,  Manabu Ishimatsu ,  Kentaro Hara

IPC分类号： G11C7/10

CPC分类号： H01L22/14 ,  G11C7/24 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of first chips, a second chip that controls the first chips, and internal wiring that connects the first chips and the second chip. The first chips each include: an optical fuse; a first latch circuit that retains information on the optical fuse; a second latch circuit that retains information on an electrical fuse, the information being supplied from the second chip through the internal wiring; and a select circuit that selects the information retained in either one of the first and second latch circuits. A redundancy determination signal is generated from the information selected. The information on the electrical fuse is transferred from the second chip to the first chips through the internal wiring.

摘要翻译： 半导体器件包括多个第一芯片，控制第一芯片的第二芯片和连接第一芯片和第二芯片的内部布线。 第一个芯片包括：一个光学保险丝; 第一锁存电路，其保存关于所述光学保险丝的信息; 第二锁存电路，其保存关于电熔丝的信息，所述信息通过所述内部布线从所述第二芯片提供; 以及选择电路，其选择保留在第一和第二锁存电路中的任一个中的信息。 从所选择的信息生成冗余确定信号。 电熔丝的信息通过内部布线从第二芯片传送到第一芯片。

公开(公告)号：US08138743B2

公开(公告)日：2012-03-20

申请号：US12357992

申请日：2009-01-22

申请人： Akira Ide

发明人： Akira Ide

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A band-gap reference voltage source circuit is constituted of a diode-pair circuit connected to a reference voltage output terminal, a first differential amplifier including a first transistor and a first operational amplifier, and a second differential amplifier including a second transistor and a second operational amplifier. The second differential amplifier operates based on a bias voltage, which is lower than a predetermined voltage, so as to forcedly pull up the level of the reference voltage output terminal via the second transistor before the first differential amplifier starts to pull up the level of the reference voltage output terminal up to the predetermined voltage via the first transistor.

摘要翻译： 带隙参考电压源电路由连接到参考电压输出端的二极管对电路，包括第一晶体管和第一运算放大器的第一差分放大器和包括第二晶体管和第二晶体管的第二差分放大器构成 运算放大器。 第二差分放大器基于低于预定电压的偏置电压进行工作，以便在第一差分放大器开始上拉第二差分放大器的电平之前经由第二晶体管强制上拉基准电压输出端子的电平 参考电压输出端经由第一晶体管直到预定电压。

公开(公告)号：US07859339B2

公开(公告)日：2010-12-28

申请号：US12285598

申请日：2008-10-09

申请人： Akira Ide

发明人： Akira Ide

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45748 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45244 ,  H03F2203/45626 ,  H03F2203/45674 ,  H03F2203/45682 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45732

摘要： A differential amplification circuit is constituted of a differential transistor pair including a pair of n-channel MOS transistors whose sources are connected together, a constant current source circuit which is connected to the sources of the differential transistor pair, a current-mirror load circuit including a pair of p-channel MOS transistors whose gates are connected together, and a bias generation circuit which generates a gate bias voltage and a drain bias voltage applied to the current-mirror load circuit in such a way that the same potential is set to both the drains of the p-channel MOS transistors. Thus, it is possible to reduce the input offset voltage without reducing the margin of operation voltage and without increasing the overall chip size.

摘要翻译： 差分放大电路由包括源极连接在一起的一对n沟道MOS晶体管的差分晶体管对，连接到差分晶体管对的源极的恒流源电路构成，电流镜负载电路包括 其栅极连接在一起的一对p沟道MOS晶体管，以及偏置产生电路，其产生施加到电流镜负载电路的栅极偏置电压和漏极偏置电压，使得将相同的电位设置为两者 p沟道MOS晶体管的漏极。 因此，可以在不降低工作电压余量的同时降低输入偏移电压，而不增加整体芯片尺寸。

公开(公告)号：US20100295618A1

公开(公告)日：2010-11-25

申请号：US12549256

申请日：2009-08-27

申请人： Akira Ide

发明人： Akira Ide

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/4565 ,  H03F2203/45416 ,  H03F2203/45521 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45674

摘要： A differential amplifier includes a main differential amplifier circuit that receives a pair of input signals and supplies a pair of output signals based on a difference between the input signals; and a bias control differential amplifier circuit that receives the pair of output signals, controls a control terminal of a current-limiting transistor making up the main differential amplifying circuit based on an offset voltage included in the output signals, and reduces the offset voltage.

摘要翻译： 差分放大器包括主差分放大器电路，其接收一对输入信号并且基于输入信号之间的差提供一对输出信号; 以及接收所述一对输出信号的偏置控制差分放大器电路，基于包括在所述输出信号中的偏移电压来控制构成所述主差分放大电路的限流晶体管的控制端，并且减小所述偏移电压。

公开(公告)号：US07633279B2

公开(公告)日：2009-12-15

申请号：US11365668

申请日：2006-03-02

申请人： Takashi Asaoka ,  Akira Ide

发明人： Takashi Asaoka ,  Akira Ide

IPC分类号： G05F3/16 ,  G05F1/10 ,  G05F3/02

CPC分类号： G05F3/262

摘要： A power supply circuit is disclosed in which the influence due to variation in the characteristics of transistors is reduced by variation alleviating devices, each connected to transistors that constitute a current mirror. The power supply circuit comprises a configuration having a current mirror to produce a reference voltage. A multiple number of transistors constitute a current mirror. Multiple variation alleviating devices are connected in series with individual transistors.

摘要翻译： 公开了一种电源电路，其中由于晶体管的特性的变化引起的影响被减小了各自连接到构成电流镜的晶体管的变化减轻装置。 电源电路包括具有电流镜以产生参考电压的配置。 多个晶体管构成电流镜。 多个变化缓解装置与各个晶体管串联连接。

公开(公告)号：US20090180341A1

公开(公告)日：2009-07-16

申请号：US12314860

申请日：2008-12-17

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G11C7/00 ,  H03L7/06 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。