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66 条记录 (耗时 0.025 秒)

    Power supply circuit
    1.
    发明授权
    Power supply circuit 有权
    电源电路

    公开(公告)号：US07633279B2

    公开(公告)日：2009-12-15

    申请号：US11365668

    申请日：2006-03-02

    申请人： Takashi Asaoka ,  Akira Ide

    发明人： Takashi Asaoka ,  Akira Ide

    IPC分类号： G05F3/16 ,  G05F1/10 ,  G05F3/02

    CPC分类号： G05F3/262

    摘要： A power supply circuit is disclosed in which the influence due to variation in the characteristics of transistors is reduced by variation alleviating devices, each connected to transistors that constitute a current mirror. The power supply circuit comprises a configuration having a current mirror to produce a reference voltage. A multiple number of transistors constitute a current mirror. Multiple variation alleviating devices are connected in series with individual transistors.

    摘要翻译： 公开了一种电源电路，其中由于晶体管的特性的变化引起的影响被减小了各自连接到构成电流镜的晶体管的变化减轻装置。 电源电路包括具有电流镜以产生参考电压的配置。 多个晶体管构成电流镜。 多个变化缓解装置与各个晶体管串联连接。

    Power supply circuit
    2.
    发明申请
    Power supply circuit 有权

    公开(公告)号：US20060197517A1

    公开(公告)日：2006-09-07

    申请号：US11365668

    申请日：2006-03-02

    申请人： Takashi Asaoka ,  Akira Ide

    发明人： Takashi Asaoka ,  Akira Ide

    IPC分类号： G05F3/16 ,  G05F3/20

    CPC分类号： G05F3/262

    摘要： A power supply circuit is disclosed in which the influence due to variation in the characteristics of transistors is reduced by variation alleviating devices, each connected to transistors that constitute a current mirror. The power supply circuit comprises a configuration having a current mirror to produce a reference voltage. A multiple number of transistors constitute a current mirror. Multiple variation alleviating devices are connected in series with individual transistors.

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US08687444B2

    公开(公告)日：2014-04-01

    申请号：US13200649

    申请日：2011-09-28

    申请人： Akira Ide ,  Hiroki Ichikawa

    发明人： Akira Ide ,  Hiroki Ichikawa

    IPC分类号： G11C7/00

    CPC分类号： G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/5606

    摘要： A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.

    摘要翻译： 按顺序测试多个存储单元。 每次通过测试检测到有缺陷的存储单元时，基于多个有缺陷的存储单元之间的相对布置关系来更新错误模式信息，并且基于多个缺陷存储器单元的至少一部分的地址来更新错误地址信息 记忆细胞 根据本发明，可以显着降低分析存储器的存储容量。 这允许在半导体器件中实现分析存储器本身，在这种情况下外部测试器不需要包括分析存储器。

    Bandgap reference circuit and method of starting bandgap reference circuit
    5.
    发明授权
    Bandgap reference circuit and method of starting bandgap reference circuit 有权
    带隙参考电路及启动带隙参考电路的方法

    公开(公告)号：US08294449B2

    公开(公告)日：2012-10-23

    申请号：US12547156

    申请日：2009-08-25

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： G05F3/28

    CPC分类号： G05F3/30

    摘要： In accordance with a bandgap circuit and a method of starting the bandgap circuit, a start signal is continuously supplied to a differential amplifier circuit to start up the differential amplifier circuit that controls a bandgap core circuit until the differential amplifier circuit has started up, and then the supply of the start signal to the differential amplifier circuit is discontinued after the differential amplifier circuit has started up.

    摘要翻译： 根据带隙电路和启动带隙电路的方法，将启动信号连续地提供给差分放大器电路，以启动控制带隙核心电路的差分放大器电路，直到差分放大器电路启动，然后 在差分放大器电路启动之后，停止向差分放大器电路提供起始信号。

    Semiconductor device, information processing system including same, and controller for controlling semiconductor device
    6.
    发明申请
    Semiconductor device, information processing system including same, and controller for controlling semiconductor device 失效
    半导体装置，包括它的信息处理系统以及用于控制半导体装置的控制器

    公开(公告)号：US20110211411A1

    公开(公告)日：2011-09-01

    申请号：US12929967

    申请日：2011-02-28

    申请人： Akira Ide

    发明人： Akira Ide

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/06 ,  G11C5/025 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.

    摘要翻译： 为了提高包括多个存储器芯片的半导体存储器的访问效率。 基于与行命令同步地接收的层地址，存储体地址和行地址以及与列命令同步地接收的层地址，存储体地址和列地址，由行选择的存储单元 访问由由芯片地址选择的核心芯片中包含的存储体地址选择的存储体中的地址和列地址。 这可以增加控制器可识别的存储体的数量，从而提高包括多个存储器芯片的半导体器件的存储器访问效率。

    Timing control circuit, timing generation system, timing control method and semiconductor memory device
    7.
    发明授权
    Timing control circuit, timing generation system, timing control method and semiconductor memory device 有权
    定时控制电路，定时生成系统，定时控制方法和半导体存储器件

    公开(公告)号：US07750712B2

    公开(公告)日：2010-07-06

    申请号：US12314207

    申请日：2008-12-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

    IPC分类号： H03H11/26

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

    摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

    摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20090086551A1

    公开(公告)日：2009-04-02

    申请号：US12285204

    申请日：2008-09-30

    申请人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Akira Ide ,  Yasuhiro Takai ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C7/00 ,  G06F11/00 ,  G06F11/10 ,  G11C8/00

    CPC分类号： G11C11/4093 ,  G06F11/1004 ,  G11C7/1006 ,  G11C7/1012 ,  G11C8/12

    摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.

    摘要翻译： 公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组 第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚 。