公开(公告)号：US20040111579A1

公开(公告)日：2004-06-10

申请号：US10338246

申请日：2003-01-08

申请人： Comax Semiconductor Inc.

发明人： Jang-Min Lin ,  Chung Chuan Wang

IPC分类号： G06F012/00

CPC分类号： G11C7/22 ,  G11C2207/2236

摘要： A method for memory device block movement. The method comprises the steps of decoding a block movement command carrying a start address, destination address and move length to generate a block movement signal, generating a first, second and third loading signal when the block movement signal is asserted, receiving the start address, destination address and move length when the loading signals are asserted respectively, during a read cycle, outputting the start address to the memory device to transfer data of a buffer length at a location beginning from the start address in the memory device into a buffer, during a write cycle, transferring the data from the buffer to a location beginning from the destination address in the memory device, subtracting the move length by the buffer length, and adding the buffer length to the start and destination address.

摘要翻译： 一种存储器件块移动的方法。 该方法包括以下步骤：解码携带起始地址，目的地地址和移动长度的块移动命令以产生块移动信号，当块移动信号被断言时产生第一，第二和第三加载信号，接收起始地址， 在读取周期期间分别确定加载信号时的目标地址和移动长度，将开始地址输出到存储器件，以将存储器件中从起始地址开始的缓冲区长度的数据传输到缓冲器中 写入周期，将数据从缓冲器传送到从存储器件中的目标地址开始的位置，将移动长度减去缓冲区长度，并将缓冲区长度添加到起始和目的地址。

公开(公告)号：US12019895B2

公开(公告)日：2024-06-25

申请号：US18125625

申请日：2023-03-23

申请人： Lodestar Licensing Group LLC

发明人： Perry V. Lea ,  Glen E. Hush

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G06F3/0647 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0685 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/2236 ,  G11C2207/2245

摘要： The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

公开(公告)号：US11646065B2

公开(公告)日：2023-05-09

申请号：US17367060

申请日：2021-07-02

申请人： Micron Technology, Inc.

发明人： John D. Porter

IPC分类号： G11C7/10 ,  G06F12/02 ,  G11C11/22

CPC分类号： G11C7/1042 ,  G06F12/0246 ,  G11C7/1039 ,  G06F2212/7211 ,  G11C11/221 ,  G11C2207/2236

摘要： An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

公开(公告)号：US20190130992A1

公开(公告)日：2019-05-02

申请号：US16044322

申请日：2018-07-24

申请人： SK hynix Inc.

发明人： Hyung-Sik WON ,  Hyungsup KIM

IPC分类号： G11C29/00 ,  G11C29/44 ,  G11C16/30 ,  G11C16/34 ,  G11C13/00

CPC分类号： G11C29/783 ,  G11C13/0097 ,  G11C16/30 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/785 ,  G11C29/835 ,  G11C2029/0411 ,  G11C2207/2236

摘要： A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

公开(公告)号：US20170329540A1

公开(公告)日：2017-11-16

申请号：US15229487

申请日：2016-08-05

申请人： SK hynix Inc.

发明人： Hee Seong KIM

IPC分类号： G06F3/06 ,  G11C11/406 ,  G11C11/4091

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0673 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4091 ,  G11C2207/2236

摘要： A semiconductor device, semiconductor system, and or method relating to a refresh operation may be provided. The semiconductor device may include an operation control signal generation circuit configured for generating an operation control signal for a target word line. The semiconductor device may include a copy operation circuit configured for performing a first copy operation of storing data of first cells coupled to an adjacent word line adjacent to the target word line, in second cells coupled to a first clone word line, based on the operation control signal.

公开(公告)号：US09805799B2

公开(公告)日：2017-10-31

申请号：US13786501

申请日：2013-03-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Joon-Ho Lee ,  Gwang-Ok Go ,  Kyung-Ho Shin ,  Mi-Hyang Lee

IPC分类号： G06F12/00 ,  G11C16/10 ,  G06F12/02

CPC分类号： G11C16/10 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C2207/2236 ,  G11C2211/5641

摘要： A nonvolatile memory device includes a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs). The device determines whether a free block can be created by copying data between memory blocks of the first area. Upon determining that the free memory block can be created by copying data between the memory blocks of the first area, the device copies the data between the memory blocks of the first area to create the free memory block. Otherwise, the device selects at least one memory block from the first area and allocates the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

公开(公告)号：US20170228192A1

公开(公告)日：2017-08-10

申请号：US15040084

申请日：2016-02-10

申请人： Micron Technology, Inc.

发明人： Jeremiah J. Willcock ,  David L. Pinney

IPC分类号： G06F3/06 ,  G11C11/4093 ,  G11C11/4091

CPC分类号： G06F3/0647 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F15/7821 ,  G11C7/1006 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/2236

摘要： The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of sub arrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

公开(公告)号：US20170147211A1

公开(公告)日：2017-05-25

申请号：US15358072

申请日：2016-11-21

申请人： Etron Technology, Inc.

发明人： Chun Shiah ,  Cheng-Nan Chang ,  Yu-Hui Sung

IPC分类号： G06F3/06 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F3/061 ,  G06F3/0644 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0893 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C16/06 ,  G11C29/06 ,  G11C29/34 ,  G11C2207/2236

摘要： A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

公开(公告)号：US20160300625A1

公开(公告)日：2016-10-13

申请号：US14742956

申请日：2015-06-18

申请人： SK hynix Inc.

发明人： Min Chang KIM

IPC分类号： G11C29/12 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C29/1201 ,  G11C29/38 ,  G11C29/40 ,  G11C2207/2236

摘要： A semiconductor apparatus may include a first data processing block electrically coupled between a first input/output pad array and a first memory array. The semiconductor apparatus may include a second data processing block electrically coupled between a second input/output pad array and a second memory array. The first test verification data and second test verification data may be generated by causing data to be respectively outputted from the first memory array and the second memory array to pass through the first data processing block and the second data processing block, according to a read command and a plurality of control signals. The first test verification data and the second test verification data may be respectively written again in the first memory array and the second memory array. A result of comparing the first test verification data and the second test verification data may be outputted through the first input/output pad array.

摘要翻译： 半导体装置可以包括电耦合在第一输入/输出焊盘阵列和第一存储器阵列之间的第一数据处理块。 半导体装置可以包括电耦合在第二输入/输出焊盘阵列和第二存储器阵列之间的第二数据处理块。 可以通过根据读取命令使得从第一存储器阵列和第二存储器阵列分别输出数据通过第一数据处理块和第二数据处理块来生成第一测试验证数据和第二测试验证数据 和多个控制信号。 可以将第一测试验证数据和第二测试验证数据分别再次写入第一存储器阵列和第二存储器阵列。 可以通过第一输入/输出焊盘阵列输出比较第一测试验证数据和第二测试验证数据的结果。

公开(公告)号：US20160085464A1

公开(公告)日：2016-03-24

申请号：US14595939

申请日：2015-01-13

申请人： SanDisk Technologies Inc.

发明人： Daniel E. Tuers ,  Abhijeet Manohar ,  Sergei Gorobets

IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F11/07

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/1048 ,  G06F11/1076 ,  G11C7/1009 ,  G11C16/08 ,  G11C2029/0411 ,  G11C2207/2236

摘要： A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

摘要翻译： 提供了一种用于片上复制收集的存储模块和方法。 在一个实施例中，存储模块设置有包括多个字线和多个数据锁存器的存储器。 存储器将数据从第一字线复制到第一数据锁存器中，并将数据从第二字线复制到第二数据锁存器中。 然后，存储器仅将来自第一数据锁存器的一些数据复制，并且仅将来自第二数据锁存器的一些数据复制到第三数据锁存器中。 之后，存储器将数据从第三数据锁存器复制到第三字线。 在另一个实施例中，提供了包括存储器和片上复制收集模块的存储模块。 提供其他实施例。