公开(公告)号：US08582373B2

公开(公告)日：2013-11-12

申请号：US12872638

申请日：2010-08-31

申请人： Timothy Hollis

发明人： Timothy Hollis

IPC分类号： G11C7/10

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/1003

摘要： Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.

摘要翻译： 显示了存储器件及其制作和操作方法。 所示的存储器件包括具有一个或多个缓冲管芯的堆叠存储器管芯。 在一个这样的存储器装置中，命令管芯通过一个或多个缓冲管芯与一个或多个下游存储器管芯通信。 一个或多个缓冲器管芯用于重复信号，并且可以潜在地提高堆叠中较高数量的存储器管芯的性能。

公开(公告)号：US20090207895A1

公开(公告)日：2009-08-20

申请号：US12379080

申请日：2009-02-12

申请人： Hwan-Wook Park ,  Young-Chan Jang

发明人： Hwan-Wook Park ,  Young-Chan Jang

IPC分类号： H04B1/38

CPC分类号： G11C8/18 ,  G11C7/1003 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C2207/2254 ,  H04L1/004

摘要： A data transceiver system may include an error corrector. The error corrector may include a plurality of delay units, each delay unit being configured to delay a corresponding data signal among a plurality of data signals by a time in response to a corresponding delay code among a plurality of delay codes and outputting the delayed data signal, an error detector configured to receive the plurality of delay codes, determine whether an error has occurred, and output an error signal according to the determination in a data frame lock operation, and a delay controller configured to set initial values of the plurality of delay codes to a predetermined value, vary and output each of the plurality of delay codes in response to a lock signal, and reset initial values the plurality of delay codes in response to the error signal in the data frame lock operation.

摘要翻译： 数据收发器系统可以包括错误校正器。 错误校正器可以包括多个延迟单元，每个延迟单元被配置为响应于多个延迟代码之间的对应的延迟代码延迟多个数据信号之间的相应数据信号，并输出延迟的数据信号 ，配置为接收所述多个延迟码的错误检测器，确定是否发生错误，并且根据数据帧锁定操作中的确定输出错误信号;以及延迟控制器，被配置为设置所述多个延迟的初始值 编码到预定值，响应于锁定信号改变并输出多个延迟码中的每一个，并且响应于数据帧锁定操作中的错误信号来复位初始值多个延迟码。

公开(公告)号：US12124741B2

公开(公告)日：2024-10-22

申请号：US18340589

申请日：2023-06-23

申请人： Lodestar Licensing Group LLC

发明人： Robert M. Walker

IPC分类号： G11C7/10 ,  G06F3/06 ,  G06F13/42

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F13/4282 ,  G11C7/1003

摘要： The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

公开(公告)号：US20240161799A1

公开(公告)日：2024-05-16

申请号：US18505372

申请日：2023-11-09

申请人： CANON KABUSHIKI KAISHA

发明人： Shuto FUNAKOSHI ,  Yohei HORIKAWA ,  Kazuma SAKATO

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1003 ,  G11C7/1066

摘要： A programmable signal processing apparatus comprises a plurality of ALUs and a control unit that performs control for configuring a targeted circuit based on received information. The plurality of ALUs include a first type of ALU with one input and multiple outputs and a second type of ALU with two inputs and one output. The first type of ALU delays input data and outputs a plurality of pieces of data with different delay amounts. The second type of ALU generates one or two delayed data and performs an operation on the one or two data. The second ALU does not delay the one or two data in a state where supply of a clock signal to a plurality of registers in the second ALU is cut off.

公开(公告)号：US20230238041A1

公开(公告)日：2023-07-27

申请号：US18089668

申请日：2022-12-28

申请人： Rambus Inc.

发明人： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC分类号： G11C7/10 ,  G11C5/04

CPC分类号： G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

摘要： A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20190252010A1

公开(公告)日：2019-08-15

申请号：US16397154

申请日：2019-04-29

申请人： International Business Machines Corporation

发明人： Steven R. Carlough ,  Susan M. Eickhoff ,  Warren E. Maule ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

IPC分类号： G11C7/10 ,  G06F3/06

CPC分类号： G11C7/109 ,  G06F3/0611 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/08 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/2245

摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

公开(公告)号：US20190035439A1

公开(公告)日：2019-01-31

申请号：US16136068

申请日：2018-09-19

申请人： MICRON TECHNOLOGY, INC.

发明人： TSUGIO TAKAHASHI ,  Zer Liang

IPC分类号： G11C7/10

CPC分类号： G11C7/1039 ,  G11C7/1003

摘要： Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory; and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US20180137896A1

公开(公告)日：2018-05-17

申请号：US15782833

申请日：2017-10-12

申请人： QUALCOMM Incorporated

发明人： Hyunsuk SHIN ,  David TEB ,  Hung VUONG ,  Venkatakrishnan GOPALAKRISHNAN

IPC分类号： G11C7/10 ,  G06F12/02 ,  G06F3/06 ,  G06F13/16

CPC分类号： G11C7/1003 ,  G06F3/0619 ,  G06F12/0246 ,  G06F13/102 ,  G06F13/1668 ,  G06F13/4247

摘要： In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

公开(公告)号：US20180011633A1

公开(公告)日：2018-01-11

申请号：US15644743

申请日：2017-07-08

申请人： Samsung Electronics Co., Ltd.

发明人： Ji-Woon PARK

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0688 ,  G11C7/1003

摘要： A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.

公开(公告)号：US09792052B2

公开(公告)日：2017-10-17

申请号：US15272933

申请日：2016-09-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John K. Debrosse ,  Blake G. Fitch ,  Michele M. Franceschini ,  Todd E. Takken ,  Daniel C. Worledge

IPC分类号： G11C11/16 ,  G06F3/06 ,  G11C7/10 ,  G11C13/00 ,  G06F13/16

CPC分类号： G06F3/0613 ,  G06F3/0602 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688 ,  G06F13/1668 ,  G11C7/10 ,  G11C7/1003 ,  G11C7/1015 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

摘要： A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.