公开(公告)号：US20040050160A1

公开(公告)日：2004-03-18

申请号：US10441892

申请日：2003-05-16

发明人： Youngsam Bae ,  Ken J. Hayworth ,  Kirill V. Shcheglov

IPC分类号： G01P015/14 ,  H01L021/28 ,  H01L021/302

CPC分类号： G01C19/5719

摘要： A split-resonator integrated-post vibratory microgyroscope may be fabricated using micro electrical mechanical systems (MEMS) fabrication techniques. The microgyroscope may include two gyroscope sections bonded together, each gyroscope section including resonator petals, electrodes, and an integrated half post. The half posts are aligned and bonded to act as a single post.

公开(公告)号：US20040018705A1

公开(公告)日：2004-01-29

申请号：US10403463

申请日：2003-03-31

发明人： Paul Frans Marie Colson ,  Sylvie Boonen ,  Eddy De Backer ,  Freddy Marcel Yvan De Pestel ,  Peter Dominique Willem Moens ,  Marnix Roger Anna Tack ,  Davy Fabien Michel Villanueva

IPC分类号： H01L021/28

CPC分类号： H01L21/743

摘要： A method for processing a low ohmic contact structure to a buried conductive layer in or below a device layer forming part of a semiconductor component is presented, whereby first a highly doped region within said device layer reaching said buried conductive layer is realised, this being followed by a step of etching a trench through said highly doped region to a final depth which extends at least to the semiconductor substrate underneath said buried conductive layer. In a variant method this trench is first pre-etched until a predetermined depth, before the highly doped region is provided. A semiconductor structure which is realised by these methods is described as well.

摘要翻译： 提出了一种用于在形成半导体部件的一部分的器件层中或其下面的掩埋导电层处理低欧姆接触结构的方法，由此首先实现到达所述掩埋导电层的所述器件层内的高度掺杂区域，这被遵循 通过将沟槽蚀刻穿过所述高掺杂区域到至少延伸到所述掩埋导电层下方的半导体衬底的最终深度的步骤。 在一种变型方法中，在提供高掺杂区域之前，首先预先蚀刻该沟槽直到预定的深度。 还描述了通过这些方法实现的半导体结构。

公开(公告)号：US20030228742A1

公开(公告)日：2003-12-11

申请号：US10131099

申请日：2002-04-25

发明人： Chao-Yuan Huang

IPC分类号： H01L021/28

CPC分类号： H01L29/665 ,  H01L21/26506

摘要： A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.

摘要翻译： 一种形成硅化物的方法。 金属层形成在硅基基板上，该硅基底板包括在栅极侧壁上具有间隔物的栅极，并且提供源极/漏极。 接下来，进行第一热处理以使金属层的部分与栅极和源极/漏极中的硅反应形成硅化物。 然后，除去任何未反应的金属和间隔物。 将含离子的硅引入源/漏。 最后，进行第二次热处理。

公开(公告)号：US20030207549A1

公开(公告)日：2003-11-06

申请号：US10136349

申请日：2002-05-02

发明人： Jason Jyh-Shyang Jenq

IPC分类号： H01L021/28

CPC分类号： H01L21/02337 ,  C23C14/08 ,  C23C14/5806 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02266 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/511 ,  H01L29/518

摘要： This invention relates to a method for forming a dielectric layer, more particularly, to a method for forming a silicate dielectric layer. The first step of the present invention is to form a silicate layer on the substrate of the wafer by using a physical vapor deposition (PVD) procedure. The silicate layer is a hafnium silicate (HfSi) layer or a zirconium silicate (ZrSi) layer. Then the silicate layer is treated to become a gate dielectric layer or an inter-layer dielectric layer which has higher a dielectric constant by using a rapid thermal annealing (RTA) procedure in a environment which is filled of nitrogen or ammonia.

摘要翻译： 本发明涉及形成电介质层的方法，更具体地说，涉及一种形成硅酸盐介电层的方法。 本发明的第一步是通过使用物理气相沉积（PVD）方法在晶片的衬底上形成硅酸盐层。 硅酸盐层是硅酸铪（HfSi）层或硅酸锆（ZrSi）层。 然后通过在填充有氮或氨的环境中使用快速热退火（RTA）方法，将硅酸盐层处理成为栅极电介质层或层间电介质层，其具有较高的介电常数。

公开(公告)号：US20030129848A1

公开(公告)日：2003-07-10

申请号：US10331794

申请日：2002-12-30

发明人： Kyu-Jin Choi

IPC分类号： H01L021/28 ,  H01L021/44 ,  H01L021/302 ,  H01L021/461

CPC分类号： H01L21/02046 ,  C23C16/0245 ,  C30B25/02 ,  C30B29/06 ,  H01J37/32082 ,  H01J2237/335

摘要： A pre-cleaning method of a substrate for a semiconductor device includes preparing a chamber, the chamber including a plasma electrode at an outside of the chamber, a power supplying system connected to the plasma electrode, a susceptor in the chamber, and an injector injecting gases into the chamber, equipping a metallic net in the chamber, the metallic net over the susceptor and grounded, disposing a substrate on the susceptor, and injecting a hydrogen gas into the chamber through the injector and supplying radio frequency power to the plasma electrode, thereby removing an oxide layer on the substrate.

摘要翻译： 用于半导体器件的衬底的预清洁方法包括制备腔室，该室包括在室外的等离子体电极，连接到等离子体电极的电源系统，腔室中的基座以及注射器 气体进入腔室，在金属网中装有金属网，并且接地，并将衬底放置在基座上，并通过注射器将氢气注入腔室，并向等离子体电极提供射频电力， 从而去除衬底上的氧化物层。

公开(公告)号：US20030129813A1

公开(公告)日：2003-07-10

申请号：US10158540

申请日：2002-05-30

申请人： Rutgers, The State University Of New Jersey

发明人： Yicheng Lu ,  Haifeng Sheng ,  Sriram Muthukumar ,  Nuri William Emanetoglu ,  Jian Zhong

IPC分类号： H01L021/28 ,  H01L021/44 ,  H01L027/095 ,  H01L029/47

CPC分类号： H01L31/0392 ,  H01L31/022408 ,  H01L31/108 ,  H01L31/1123 ,  Y02E10/50

摘要： In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

摘要翻译： 在本发明中，提供了在n型ZnO和Mg x Zn 1-x O外延膜上制造的肖特基UV光电探测器等半导体器件。 ZnO和MgxZn1-xO膜在R平面蓝宝石衬底上生长，肖特基二极管分别用银和铝作为肖特基和欧姆接触金属制作在ZnO和Mg x Zn 1-x O膜上。 肖特基二极管具有圆形图案，其中内圆是肖特基接触，外环是欧姆接触。 Ag肖特基接触图案使用标准剥离技术制造，而Al欧姆接触图案是使用湿化学蚀刻法形成的。 与其感光对手相比，这些检测器显示低频光响应，高速光响应，较低的漏电流和低噪声性能。 本发明还可应用于光学调制器，金属半导体场效应晶体管（MESFET）等。

公开(公告)号：US20030119271A1

公开(公告)日：2003-06-26

申请号：US10036714

申请日：2001-12-21

发明人： Sanjeev Aggarwal ,  Stephen R. Gilbert ,  Scott R. Summerfelt

IPC分类号： H01L021/20 ,  H01L021/28 ,  H01L021/44

CPC分类号： H01L21/02197 ,  H01L21/02271 ,  H01L21/31691 ,  H01L27/10811 ,  H01L28/55 ,  H01L28/75

摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

公开(公告)号：US20030042608A1

公开(公告)日：2003-03-06

申请号：US10234734

申请日：2002-09-03

发明人： Jong-Chol Seol

IPC分类号： H01L033/00 ,  H01L023/48 ,  H01L029/40 ,  H01L021/28

CPC分类号： H01L24/03 ,  H01L2224/04042 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01S5/02276 ,  H01S5/0425 ,  H01L2924/00

摘要： The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

摘要翻译： 本发明提供一种用于光学半导体器件的焊盘，包括：形成在半导体衬底上的由Si 3 N 4制成的第一辅助粘合层; 形成在第一辅助粘合剂层上的由苯并环丁烯制成的焊盘层; 在所述接合焊盘层上形成由Si 3 N 4制成的第二辅助粘合层; 以及形成在所述第二辅助粘合剂层上的金属电极层。

公开(公告)号：US20030013284A1

公开(公告)日：2003-01-16

申请号：US09904894

申请日：2001-07-16

申请人： MOTOROLA, INC.

发明人： Rudy M. Emrick ,  Nestor J. Escalera

IPC分类号： H01L021/28 ,  H01L021/44 ,  H01L031/0328

CPC分类号： H03F3/605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H03F3/211 ,  H03F3/602

摘要： Power combining amplifiers using two different monocrystalline materials in a monolithic device are provided. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

摘要翻译： 提供了在单片设备中使用两种不同单晶材料的功率组合放大器。 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20020197830A1

公开(公告)日：2002-12-26

申请号：US10178853

申请日：2002-06-25

发明人： Hiroshi Watanabe ,  Masayoshi Koike

IPC分类号： C30B023/00 ,  C30B025/00 ,  C30B028/12 ,  C30B028/14 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36 ,  H01L021/3205 ,  H01L021/28

CPC分类号： C30B25/02 ,  C23C16/303 ,  C23C16/4488 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262

摘要： The method of the invention for producing a Group III nitride compound semiconductor, employing an etchable substrate which is produced from a material other than the Group III nitride compound semiconductor, includes stacking one or more layers of the Group III nitride compound semiconductor on one face of the substrate and etching the other face of the substrate while stacking one or more semiconductor layers or after completion of stacking one or more semiconductor layers, to thereby reduce the thickness of most of the substrate. The apparatus of present invention for producing a semiconductor through vapor phase growth, contains a substrate for vapor-phase-growing the semiconductor; a source-supplying system for supplying a source for vapor phase growth of the semiconductor; and an etchant-supplying system, wherein the source-supplying system and the etchant-supplying system are isolated through placement of the substrate.

摘要翻译： 本发明的用于制造III族氮化物化合物半导体的方法，采用由III族氮化物化合物半导体以外的材料制成的可蚀刻衬底，包括将一层或多层III族氮化物化合物半导体堆叠在 并且在堆叠一个或多个半导体层之后或者在堆叠一个或多个半导体层之后蚀刻衬底的另一个面，从而减小了大部分衬底的厚度。 用于通过气相生长生产半导体的本发明的装置包含用于使半导体气相生长的衬底; 用于提供半导体气相生长源的源供应系统; 以及蚀刻剂供应系统，其中通过放置基板来隔离源供应系统和蚀刻剂供应系统。