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公开(公告)号：US09917195B2
公开(公告)日：2018-03-13
申请号：US14812425
申请日：2015-07-29
Applicant: International Business Machines Corporation , GlobalFoundries, Inc. , STMicroelectronics, Inc.
Inventor： Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
CPC classification number: H01L29/1033 , H01L21/30621 , H01L29/1054 , H01L29/20 , H01L29/41791 , H01L29/66522 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
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公开(公告)号：US09917194B2
公开(公告)日：2018-03-13
申请号：US15365640
申请日：2016-11-30
Applicant: STMicroelectronics, Inc.
Inventor： Nicolas Loubet , Pierre Morin
IPC: H01L29/78 , H01L27/088 , H01L29/49 , H01L29/06 , H01L29/417 , H01L29/10 , H01L29/66 , H01L29/161
CPC classification number: H01L29/785 , H01L27/0886 , H01L29/0623 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/41791 , H01L29/495 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/7849 , H01L2029/7858
Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
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公开(公告)号：US09905706B2
公开(公告)日：2018-02-27
申请号：US15260206
申请日：2016-09-08
Applicant: STMICROELECTRONICS, INC.
Inventor： Qing Liu , John H. Zhang
IPC: H01L21/30 , H01L29/84 , H01H59/00 , B82B3/00 , H01H1/00 , H01H49/00 , H01L21/02 , H01L21/306 , H01H50/00
CPC classification number: H01L29/84 , B82B3/00 , H01H1/0094 , H01H49/00 , H01H50/005 , H01H59/0009 , H01H2001/0084 , H01L21/02532 , H01L21/30608
Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.
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公开(公告)号：US09899170B2
公开(公告)日：2018-02-20
申请号：US15044762
申请日：2016-02-16
Applicant: STMicroelectronics, Inc.
Inventor： Thomas L. Hopkins
CPC classification number: H01H35/02 , D06F75/26 , G05B9/02 , H01H35/14 , H01H2231/012
Abstract: A protective circuit for an apparatus includes an accelerometer having an output and a microcontroller coupled to the output of the accelerometer. The protective circuit also includes a switch for controlling the apparatus coupled to an output of the microcontroller and a load coupled to the switch. A power source is coupled to the load and the switch. In operation the microcontroller is cable of sending a signal to the switch to turn of power to the load when a dangerous condition as detected from the accelerometer data has occurred.
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公开(公告)号：US09887196B2
公开(公告)日：2018-02-06
申请号：US14583842
申请日：2014-12-29
Applicant: International Business Machines Corporation , GlobalFoundries, Inc. , STMicroelectronics, Inc.
Inventor： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC: H01L27/092 , H01L29/10 , H01L27/12 , H01L21/84 , H01L29/165 , H01L21/308 , H01L21/8238 , H01L29/16 , H01L29/06 , H01L21/033 , H01L29/78
CPC classification number: H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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Patent Agency Ranking
公开(公告)号：US09871669B2
公开(公告)日：2018-01-16
申请号：US14559779
申请日：2014-12-03
Applicant: STMicroelectronics, Inc.
Inventor： Oleg Logvinov , Bo Zhang , Huijuan Liu , Michael John Macaluso , James D. Allen
IPC: H04L12/18 , H04L12/40 , H04L29/08 , H04B3/54 , B60R16/023
CPC classification number: H04L12/1886 , B60R16/023 , H04B3/542 , H04L12/1863 , H04L12/1881 , H04L12/40 , H04L12/40032 , H04L67/12 , H04L2012/40215 , H04L2012/40273
Abstract: An embodiment is a powerline communications (PLC) apparatus including a communications interface that implements a first communication protocol including of a transceiver that communicates over an electrical power distribution wiring of a vehicle. The first communication protocol includes a powerline communications automotive network (PLCAN) delimiter type (DT) (PLCAN-DT), and a PLCAN variant length field in a frame control comprising payload length, a number of symbols used, a PHY block size, and a number of repetitions used, wherein broadcast addressing is used in the network to transmit messages.
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公开(公告)号：US09870535B2
公开(公告)日：2018-01-16
申请号：US15074188
申请日：2016-03-18
Inventor： Mahesh Chowdhary , Arun Kumar , Ghanapriya Singh , Kashif R. J. Meer , Indra Narayan Kar , Rajendar Bahl
CPC classification number: G06N7/005 , G06F17/30477
Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.
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公开(公告)号：US09838963B2
公开(公告)日：2017-12-05
申请号：US15365600
申请日：2016-11-30
Applicant: STMICROELECTRONICS, INC.
Inventor： Liwen Chu , George A. Vlantis
CPC classification number: H04W52/0209 , H04W8/22 , H04W52/0206 , H04W52/0216 , H04W52/0222 , H04W52/0229 , H04W84/12 , H04W88/02 , H04W88/08 , Y02D70/00 , Y02D70/142
Abstract: A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAs) reduces power consumption and increases battery life of power efficient low power STAs by decreasing the amount of time that a power efficient low power STA remains in an awake state. After indicating power efficient low power operation during association with an AP supporting such operation, the power efficient low power STA may enter the doze state from the time that the power efficient low power STA sends a PS-Poll until the power efficient low power STA receives the buffered DATA frame from the AP. While implementing the power efficient PS-Poll method, the AP can send the buffered DATA frame to the STA SIFS after the AP sends an ACK to the received PS-Poll from the STA.
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公开(公告)号：US09825055B2
公开(公告)日：2017-11-21
申请号：US14802996
申请日：2015-07-17
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang
IPC: H01L21/04 , H01L27/12 , H01L29/66 , H01L27/11 , H01L27/092 , H01L29/161 , H01L29/78 , H01L23/528 , H01L27/112 , H01L21/84
CPC classification number: H01L27/1211 , H01L21/266 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823871 , H01L21/845 , H01L23/528 , H01L27/0924 , H01L27/1104 , H01L27/1108 , H01L27/11213 , H01L29/0649 , H01L29/161 , H01L29/66795 , H01L29/7831 , H01L29/7838 , H01L29/7849 , H01L2924/0002 , H01L2924/00
Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.
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公开(公告)号：US09824979B2
公开(公告)日：2017-11-21
申请号：US14982018
申请日：2015-12-29
Applicant: STMICROELECTRONICS, INC.
Inventor： Godfrey Dimayuga , Frederick Arellano , Michael Tabiera
IPC: H01L23/552 , H01L21/56 , H01L23/31 , H01L23/00
CPC classification number: H01L23/552 , H01L21/561 , H01L21/563 , H01L23/3114 , H01L23/3128 , H01L24/43 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L2224/32225 , H01L2224/48227 , H01L2224/48249 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2224/83 , H01L2224/85 , H01L2224/45099 , H01L2224/32245 , H01L2224/48247
Abstract: An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the conductive areas. An integrated circuit (IC) is carried by the substrate. Bond wires are coupled between the IC and respective ones of the conductive areas. An encapsulating material is over the IC and adjacent portions of the substrate. A conductive layer is on the encapsulating material, and at least one conductive body is coupled between the at least one edge conductive area and the conductive layer.
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