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    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    61.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体封装结构及其制造方法

    公开(公告)号：US20130049198A1

    公开(公告)日：2013-02-28

    申请号：US13366367

    申请日：2012-02-06

    Applicant: Tsung-Jen Liao ,  Cheng-Tang Huang ,  Mei-Fang Peng

    Inventor： Tsung-Jen Liao ,  Cheng-Tang Huang ,  Mei-Fang Peng

    IPC: H01L23/48 ,  H01L21/78

    CPC classification number: H01L21/78 ,  H01L21/568 ,  H01L23/3185 ,  H01L23/48 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor package structure is provided. A chip is provided. An active surface of the chip is disposed on a carrier. A molding compound is formed on the carrier with a metal layer disposed thereon. The metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities. The protrusions are embedded in the molding compound. The metal layer is patterned to form multiple pads on a portion of the molding compound. The carrier and the molding compound are separated. Multiple through holes are formed on the molding compound exposing the protrusions. A redistribution layer is formed on the molding compound and the active surface of the chip. Multiple solder balls are formed on the redistribution layer. A portion of the solder balls are correspondingly disposed to the pads.

    Abstract translation: 提供一种制造半导体封装结构的方法。 提供了一个芯片。 芯片的有源表面设置在载体上。 在其上设置有金属层的载体上形成模塑料。 金属层具有上表面和下表面，在上表面上形成有多个空腔，并且形成在下表面上并对应于空腔的多个突起。 突起嵌入模塑料中。 金属层被图案化以在模制化合物的一部分上形成多个焊盘。 载体和模塑料分离。 在暴露突起的模塑料上形成多个通孔。 在模塑料和芯片的活性表面上形成再分布层。 在再分布层上形成多个焊球。 焊球的一部分相应地设置在焊盘上。

    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    62.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体封装结构及其制造方法

    公开(公告)号：US20130049197A1

    公开(公告)日：2013-02-28

    申请号：US13352346

    申请日：2012-01-18

    Applicant: Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    Inventor： Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    IPC: H01L23/498 ,  H01L21/60

    CPC classification number: H01L23/13 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2225/1041 ,  H01L2225/1058

    Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

    Abstract translation: 半导体封装结构的制造方法包括：提供具有多个通孔的第一电介质层; 提供具有多个导电通孔和含芯片的开口的第二电介质层; 将第二电介质层层压到第一介电层上; 将芯片设置在含芯片的开口中并将芯片的后表面粘附到由含芯片的开口暴露的第一介质层上; 在所述第二电介质层上形成再分布电路层，其中所述再分布电路层的一部分从所述第二电介质层延伸到所述芯片的有源表面和所述导电通孔，使得所述芯片将所述导电通孔电连接到所述部分再分布电路层 ; 在第一介电层上形成多个焊球，其中焊球位于通孔中，并通过导电通孔和再分布电路层将芯片电连接。

    Technique for reducing physical layer (PHY) overhead in wireless LAN systems
    65.
    发明授权
    Technique for reducing physical layer (PHY) overhead in wireless LAN systems 有权
    用于减少无线局域网系统中物理层（PHY）开销的技术

    公开(公告)号：US08027366B1

    公开(公告)日：2011-09-27

    申请号：US12703288

    申请日：2010-02-10

    Applicant: Hsiao-Cheng Tang ,  Ravi Narasimhan ,  Hemanth Sampath

    Inventor： Hsiao-Cheng Tang ,  Ravi Narasimhan ,  Hemanth Sampath

    IPC: H04L12/56 ,  H04J1/16

    CPC classification number: H04L1/0079 ,  H04L1/0083 ,  H04L1/1607

    Abstract: A physical layer (PHY) packet aggregation technique may be used to reduce the percentage of PHY overhead in data transmission in order to achieve better PHY efficiency and higher throughput. Higher layer packets in an upper layer data queue may be fragmented into appropriate small-size sub-packets, which include a body encapsulated by a MAC header and an FCS field. The sub-packets are then concatenated to form the data field of an aggregated PHY packet. Since each of the sub-packets contains its own MAC (Media Access Control) header and FCS (Frame Check Sequence) field, the receiver can identify and flag erroneous sub-packets on an individual basis. The receiver may transmit a block ACK, which includes the acknowledgement status for each of the sub-packets in the aggregated PHY packet, to the transmitter. The transmitter may resend only the erroneous sub-packet(s).

    Abstract translation: 可以使用物理层（PHY）分组聚合技术来减少数据传输中PHY开销的百分比，以便实现更好的PHY效率和更高的吞吐量。 上层数据队列中的较高层分组可能被分段成适当的小尺寸子分组，其包括由MAC头部和FCS字段封装的主体。 然后，子分组被级联以形成聚合的PHY分组的数据字段。 由于每个子分组包含其自身的MAC（媒体访问控制）报头和FCS（帧校验序列）字段，所以接收机可以单独地识别和标记错误的子分组。 接收机可以向发射机发送包括聚合PHY分组中的每个子分组的确认状态的块ACK。 发射机可以仅重新发送错误的子分组。

    Dye-sensitized solar cell and photoanode thereof
    66.
    发明申请
    Dye-sensitized solar cell and photoanode thereof 审中-公开
    染料敏化太阳能电池及其光电阳极

    公开(公告)号：US20110100462A1

    公开(公告)日：2011-05-05

    申请号：US12654998

    申请日：2010-01-13

    Applicant: Wei-Cheng Tang ,  Ming-Si Wu ,  Kuan-Wei Lee ,  Hsin-Yi Chen

    Inventor： Wei-Cheng Tang ,  Ming-Si Wu ,  Kuan-Wei Lee ,  Hsin-Yi Chen

    IPC: H01L51/46 ,  H01L51/48

    CPC classification number: H01M14/005 ,  C09B23/105 ,  C09B57/00 ,  Y02E10/542 ,  Y02P70/521

    Abstract: A dye-sensitized solar cell, a photoanode thereof, and a method for manufacturing the same are disclosed. The photoanode of the dye-sensitized solar cell of the present invention is prepared by a porous semiconductor layer absorbing two kinds of organic sensitized dyes, and one organic sensitized dye is represented by the following formula (I): wherein, D1, D2, R1, R2, R3, R4, B, and n are defined the same as the specification.These two kinds of the organic sensitized dyes have comparative absorption peaks, so the photoanode of the present invention can absorb solar spectrum with larger wavelength range. Hence, the dye-sensitized solar cell using the photoanode of the present invention has excellent photoelectric conversion efficiency.

    Abstract translation: 公开了染料敏化太阳能电池及其光电阳极及其制造方法。 本发明的染料敏化太阳能电池的光电阳极通过吸收两种有机增感染料的多孔半导体层制备，一种有机增感染料由下式（I）表示：其中，D1，D2，R1 R2，R3，R4，B和n定义与说明书相同。 这两种有机敏化染料具有比较的吸收峰，因此本发明的光电阳极可以吸收更大波长范围的太阳光谱。 因此，使用本发明的光电阳极的染料敏化太阳能电池具有优异的光电转换效率。

    Voltage booster by isolation and delayed sequential discharge
    67.
    发明授权
    Voltage booster by isolation and delayed sequential discharge 有权
    电压升压器通过隔离和延迟顺序放电

    公开(公告)号：US07760558B2

    公开(公告)日：2010-07-20

    申请号：US12014454

    申请日：2008-01-15

    Applicant: Chin-Ghee Ch'ng ,  Kuan-Cheng Tang

    Inventor： Chin-Ghee Ch'ng ,  Kuan-Cheng Tang

    IPC: G11C7/00

    CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/30

    Abstract: Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can be used to prevent boosting of one capacitor from negatively affecting a charge of the other adjacent capacitor to improve the efficiency of the voltage booster. A voltage booster circuit can accurately boost a supply voltage with a suitable number of boosting stages depending on a level of the supply voltage being provided. Since boosters contain a suitable number of boosting stages, the boosters can discharge a boosted voltage sequentially. With this sequential discharge method, memory cells can not have a hot switching problem.

    Abstract translation: 公开了用于提高存储器单元的读取模式操作的升压器的效率并且安全地放电升压的电压的系统和方法。 该系统包括串联耦合的多个升压级，包括多个升压电容器，多个隔离器。 隔离器可用于防止一个电容器的升压对其他相邻电容器的电荷产生负面影响，以提高升压器的效率。 升压电路可以根据所提供的电源电平的水平，以适当数量的升压级来精确地提高电源电压。 由于增压器包含适当数量的升压级，所以增压器可以依次放电升压。 利用这种顺序放电方法，存储器单元不能具有热切换问题。

    Connection structure and data processing apparatus therewith
    68.
    发明授权
    Connection structure and data processing apparatus therewith 有权
    连接结构和数据处理设备

    公开(公告)号：US07755883B2

    公开(公告)日：2010-07-13

    申请号：US11907211

    申请日：2007-10-10

    Applicant: Chih Chiang Hsu ,  Chia Cheng Tang ,  Chien Jung Su

    Inventor： Chih Chiang Hsu ,  Chia Cheng Tang ,  Chien Jung Su

    IPC: G06F1/16

    CPC classification number: F16B37/043 ,  G06F1/1616 ,  G06F1/1662

    Abstract: The invention provides a connection structure installed in a data processing apparatus. The data processing apparatus includes a keyboard and a base. The keyboard includes a bottom. The base includes a top plate. The connection structure connects the bottom and the top plate. The connection structure includes a mounted boss and a mounting hole. The mounted boss is disposed on the bottom of the keyboard. The mounted boss includes a groove. The mounting hole is disposed on the top plate of the base. The mounting hole includes a protrusion. When the bottom of the keyboard is assembled to the top of the base, the mounted boss would fit into the mounting hole, such that the protrusion is locked with the groove.

    Abstract translation: 本发明提供一种安装在数据处理装置中的连接结构。 数据处理装置包括键盘和基座。 键盘包括一个底部。 底座包括顶板。 连接结构连接底板和顶板。 连接结构包括安装的凸台和安装孔。 安装的凸台设置在键盘的底部。 安装的凸台包括凹槽。 安装孔设置在基座的顶板上。 安装孔包括突起。 当键盘的底部组装到基座的顶部时，安装的凸台将装配到安装孔中，使得突起与凹槽锁定。

    DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF
    70.
    发明申请
    DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF 审中-公开
    DIE附件包装结构及其方法

    公开(公告)号：US20090302465A1

    公开(公告)日：2009-12-10

    申请号：US12330764

    申请日：2008-12-09

    Applicant: Cheng-Tang HUANG

    Inventor： Cheng-Tang HUANG

    IPC: H01L21/50 ,  H01L21/768 ,  H01L23/498

    CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/83191 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

    Abstract: A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer.

    Abstract translation: 提供了一种管芯重排封装结构，包括一个管芯; 封装结构围绕模具的四个侧面被覆盖以暴露模具的活性表面和反面; 在封装结构和芯片的有源表面上形成图案化保护层，并且焊盘被暴露; 扇出图案化金属层的一端电连接焊盘，另一端延伸以覆盖图案化的保护层; 图案化的第二保护层被提供以覆盖图案化的金属层以暴露图案化金属层的部分表面; 图案化的UBM层形成在图案化金属层的暴露表面上; 并且在图案化的UBM层上形成导电部件，并且电连接图案化的金属层。

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