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    METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDER BUMP METALLURGIC LAYER CONNECTING METAL LEAD
    5.
    发明申请
    METHOD OF DIE REARRANGEMENT PACKAGE STRUCTURE HAVING PATTERNED UNDER BUMP METALLURGIC LAYER CONNECTING METAL LEAD 审中-公开
    具有连接金属引线的金属层连接图案的封装结构的方法

    公开(公告)号：US20110003431A1

    公开(公告)日：2011-01-06

    申请号：US12882324

    申请日：2010-09-15

    Applicant: Cheng-Tang HUANG

    Inventor： Cheng-Tang HUANG

    IPC: H01L21/50

    CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/83191 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

    Abstract: A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer.

    Abstract translation: 提供了一种管芯重排封装结构，包括一个管芯; 封装结构围绕模具的四个侧面被覆盖以暴露模具的活性表面和反面; 在封装结构和芯片的有源表面上形成图案化保护层，并且焊盘被暴露; 扇出图案化金属层的一端电连接焊盘，另一端延伸以覆盖图案化的保护层; 图案化的第二保护层被提供以覆盖图案化的金属层以暴露图案化金属层的部分表面; 图案化的UBM层形成在图案化金属层的暴露表面上; 并且在图案化的UBM层上形成导电部件，并且电连接图案化的金属层。

    Semiconductor package structure and manufacturing method thereof
    8.
    发明授权
    Semiconductor package structure and manufacturing method thereof 有权
    半导体封装结构及其制造方法

    公开(公告)号：US09196553B2

    公开(公告)日：2015-11-24

    申请号：US13352346

    申请日：2012-01-18

    Applicant: Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    Inventor： Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    IPC: H01L23/60 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L21/683

    CPC classification number: H01L23/13 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2225/1041 ,  H01L2225/1058

    Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

    Abstract translation: 半导体封装结构的制造方法包括：提供具有多个通孔的第一电介质层; 提供具有多个导电通孔和含芯片的开口的第二电介质层; 将第二电介质层层压到第一介电层上; 将芯片设置在含芯片的开口中并将芯片的后表面粘附到由含芯片的开口暴露的第一介质层上; 在所述第二电介质层上形成再分布电路层，其中所述再分布电路层的一部分从所述第二电介质层延伸到所述芯片的有源表面和所述导电通孔，使得所述芯片将所述导电通孔电连接到所述部分再分布电路层 ; 在第一介电层上形成多个焊球，其中焊球位于通孔中，并通过导电通孔和再分布电路层将芯片电连接。

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