公开(公告)号：US20080264684A1

公开(公告)日：2008-10-30

申请号：US12003669

申请日：2007-12-28

Applicant: Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

Inventor： Myung Sam Kang ,  Byoung Youl Min ,  Je Gwang Yoo ,  Jung Hyun Park ,  Chang Sup Ryu ,  Jin Yong Ahn

IPC: H05K3/10 ,  H05K1/00 ,  H05K1/11

CPC classification number: H05K3/428 ,  H05K3/205 ,  H05K3/383 ,  H05K3/384 ,  H05K3/4602 ,  H05K3/4658 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/1536 ,  Y10T29/49155

Abstract: Disclosed herein is a carrier member for transmitting circuits, which is a component of a coreless printed circuit board having circuit patterns embedded therein, and which can be used to provide a high-density and highly reliable printed circuit board by forming protrusions only on the lower ends of the circuit patterns, a coreless printed circuit board using the carrier member, and methods of manufacturing the carrier member and the coreless printed circuit board.

Abstract translation: 本文公开了一种用于传输电路的载体构件，其是具有嵌入其中的电路图案的无芯印刷电路板的部件，其可用于通过仅在下部形成突起来提供高密度和高可靠性的印刷电路板 电路图案的端部，使用载体部件的无芯印刷电路板，以及制造载体部件和无芯印刷电路板的方法。

公开(公告)号：US07410869B2

公开(公告)日：2008-08-12

申请号：US11480380

申请日：2006-07-05

Applicant: Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

Inventor： Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/32115 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Abstract translation: 在制造诸如闪速存储器件的半导体器件的方法中，形成具有开口的绝缘图案以部分地暴露衬底的表面。 第一硅层形成在基板的露出表面部分和绝缘图案上。 第一硅层具有覆盖衬底的先前暴露部分的开口接缝。 在足以诱导硅迁移的温度下进行在基板上的热处理，以便通过硅迁移使开放的接缝闭合。 然后在第一硅层上形成第二硅层。 因此，可以提高从第一和第二硅层获得的浮栅的表面轮廓。

公开(公告)号：US20080105915A1

公开(公告)日：2008-05-08

申请号：US11605317

申请日：2006-11-29

Applicant: Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

Inventor： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

Abstract translation: 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层，设置在衬底的表面部分中以限定有源区的场绝缘图案，每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构，以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。

公开(公告)号：US20080098597A1

公开(公告)日：2008-05-01

申请号：US11976072

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

Abstract translation: 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。

公开(公告)号：US20080098596A1

公开(公告)日：2008-05-01

申请号：US11976071

申请日：2007-10-19

Applicant: Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

Inventor： Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

IPC: H05K3/20

CPC classification number: H05K3/20 ,  H05K3/205 ,  H05K3/207 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49163

Abstract: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.

Abstract translation: 公开了一种形成转录电路的方法及其制造方法。 一种形成转录电路的方法，其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案，将导电材料填充到凹版图案中，以及通过将载体压载到载体上而将载体转移到 使得载体面向具有填充有导电材料的模板的表面的模板，使得可以形成可以使用现有设备转录成绝缘板的转录电路，由此可以降低成本。

公开(公告)号：US20080044981A1

公开(公告)日：2008-02-21

申请号：US11769042

申请日：2007-06-27

Applicant: Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

Inventor： Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

IPC: H01L21/3205 ,  H01L21/762

CPC classification number: H01L21/76232

Abstract: Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask. The trench is substantially narrower than the second opening and has a sidewall that has a second inclination angle that is substantially larger than the first inclination angle.

Abstract translation: 提供制造包括在半导体衬底上形成掩模图案的半导体器件的方法。 掩模图案限定了至少部分地暴露半导体衬底并且在衬垫氧化物层图案上包括衬垫氧化物层和氮化物层图案的第一开口。 氮化物层具有基本上大于衬垫氧化物层图案的线宽。 通过至少部分去除通过第一开口暴露的半导体衬底的一部分，形成连接到第一开口的第二开口。 第二开口具有具有第一倾斜角并且至少部分地暴露半导体衬底的侧壁。 通过使用掩模图案蚀刻通过第二开口暴露的半导体衬底的一部分来形成连接到第二开口的沟槽作为蚀刻掩模。 沟槽基本上比第二开口窄，并且具有侧壁，该侧壁的第二倾斜角度基本上大于第一倾斜角度。

公开(公告)号：USD560181S1

公开(公告)日：2008-01-22

申请号：US29269992

申请日：2006-12-12

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：USD539771S1

公开(公告)日：2007-04-03

申请号：US29241757

申请日：2005-10-31

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：USD539250S1

公开(公告)日：2007-03-27

申请号：US29241756

申请日：2005-10-31

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：US20070065986A1

公开(公告)日：2007-03-22

申请号：US11524402

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/00

CPC classification number: H05K3/4652 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0574 ,  H05K2203/063 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的一侧上形成第一电路图案; （b）在第一干膜上层压第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在要形成空腔的区域外的区域上层叠电介质层，所述电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的方法可以通过减小封装上的封装上的衬底的厚度来安装多个集成电路。